Stacked wafer electronic package

4956746
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Inventors

Gates, Jr., Louis E.
Finnila, Charles A.

Application #

329991

Filed

Mar-29-1989

Published

Sep-11-1990

Current US Class

165/104.33
257/714
257/E25.013
361/689
361/699
361/744

International Classes

H05K 007/20

Field of Search

174/15.1 211/41 357/76 357/82 165/80.4 165/104.33 361/393-396 361/382-388 361/412 361/413

Assignee

Hughes Aircraft Company (Los Angeles, CA)

Examiners

Tolin; Gerald P.

Attorney, Agent or Firm

Alkov; Leonard A., Denson-Low; Wanda K.

US Patent References

4158875   Air cooling equipm...
4493010   Electronic packagi...
4603344   Rotating rectifier as...
4712158   Cooling system for...
4841355   Three-dimensional...

Referenced by:

View Backward References

Other References

Universal Electronic Package, Goldmann, IBM Tech. Discl. Bull., vol. 27, No. 6, Nov. 1984, p. 3335.

Citation

Cite This Patent

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Abstract
The electronic package (10) is comprised of a plurality of support plates (12-24), each of which has a plenum therein and preferably webs extending into the plenum for fluid flow control and heat transfer. A wafer (104) is mounted in a recess (100) in the support plate (12) so that fluid in the plenum (52) directly cools the wafer. Electrical connection is by flexible cable (108) to an exterior printed wiring board (40). The package may have any selected number of support plates, and each support plate may carry one full-sized wafer for compact packaging.
 
Claims
What is claimed is:

1. An electronic package comprising:

at least first and second support plates and a bottom support plate, each of said support plates having a support surface thereon, a semiconductor wafer directly supported on said support surface of each of said support plates, each of said support plates having a plenum formed therein, said first and second support plates and said bottom support plate being stacked so that said first support plate is on tope of said second support plate so that said plenum of said first support plate directly faces said support surface of said second support plate;

a top plate engaging on and covering said first support plate and a bottom plate beneath and covering the bottom of said bottom support plate, said top plate, said support plates and said bottom plate being stacked;



Description
FIELD OF THE INVENTION

This invention is directed to a structure which comprises a plurality of support plates which each support an integrated circuit wafer and permit connection to the wafers. Passages and plenums in the support plates control the flow of coolant fluid past the wafers and support plates.

BACKGROUND OF THE INVENTION

The conventional way of supporting and protecting individual very large-scale integrated circuit chips and gate array chips consists of mounting such chips in a single chip package or in a multi-chip hybrid circuit package. The packages are then mounted on printed wiring boards and associated with a plurality of other such printed wiring boards. The printed wiring boards are protected and enclosed in a comparatively large enclosure. Volume efficiency of such electronic packaging is very low because there is a great deal of printed wiring board, enclosure and package for each chip. Similarly, the weight is high for the same reasons. Circuit performance is impaired by long signal lines with concomitant undesirable impedance, crosstalk, excessive capacitance, uneven power forms, voltage drops and other electrical problems. In order to reduce the very great number of interconnections external to the integrated circuit in conventional packaging, in accordance with this invention it is practical to interconnect circuit elements at the wafer level, providing element yields are sufficiently high to permit this. The net number of external connections from a complex wafer can be vastly lower than if the elements are separated and individually packaged as chips. This however, then requires that wafers be interconnected directly, rather than as individual chips in packages. Thus, there is need for providing an interconnection method which permits the dense packaging of high density, integrated circuit wafers, together with permitting connections to the wafers and cooling of the wafers while the wafers are well protected from hostile environment.
 
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