Microwave-activated etching of dielectric layers

6015761
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Inventors

Merry, Walter Richardson
Brown, William
Herchen, Harald
Welch, Michael D.

Application #

672469

Filed

Jun-26-1996

Published

Jan-18-2000

Current US Class

216/69
216/79
257/E21.252
257/E21.578
257/E21.579
438/723
438/727
438/743

International Classes

H01L 021/00

Field of Search

216/69 216/70 216/79 438/723-725 438/726 438/728 438/727 438/743 204/298.38 204/298.37 156/345

Assignee

Applied Materials, Inc. (Santa Clara, CA)

Examiners

Powell; William

Attorney, Agent or Firm

Janah; Ashok

US Patent References

4175235   Apparatus for the p...
4462863   Microwave plasma...
4581100   Mixed excitation pl...
4673456   Microwave apparat...
4687544   Method and appar...
4764245   Method for generati...
4828649   Method for etching...
4844773   Process for etching...
4851630   Microwave reactive...
4857140   Method for etching...
4867841   Method for etch of...
4878994   Method for etching...
4983254   Processing for strip...
5201994   Dry etching method
5228950   Dry process for rem...
5286344   Process for selectiv...
5326427   Method of selectivel...
5423945   Selectivity for etchi...
5445710   Method of manufac...
 

Referenced by:

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Citation

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Abstract
A microwave-activated plasma process for etching dielectric layers (20) on a substrate (25) with excellent control of the shape and cross-sectional profile of the etched features (40), high etch rates, and good etching uniformity, is described. A process gas comprising (i) fluorocarbon gas (preferably CF.sub.4), (ii) inorganic fluorinated gas (preferably NF.sub.3), and (iii) oxygen, is used. The process gas is introduced into a plasma zone (55) remote from a process zone (60) and microwaves are coupled into the plasma zone (55) to form a microwave-activated plasma. The microwave-activated plasma is introduced into the process zone (60) to etch the dielectric layer (20) on the substrate (25) with excellent control of the shape of the etched features.
 
Claims
What is claimed is:

1. A method of etching a dielectric layer on a substrate, the method comprising the steps of:

(a) placing the substrate having the dielectric layer, in a process zone;

(b) introducing into a remote zone that is remote from the process zone, a process gas comprising (i) fluorocarbon gas, (ii) inorganic fluorinated gas, and (iii) O.sub.2 ;

(c) forming microwave-activated species from the process gas by coupling microwaves into the remote zone; and

(d) introducing the microwave-activated species into the process zone to etch the dielectric layer on the substrate.

2. The method of claim 1, wherein the volumetric flow rates of fluorocarbon gas, inorganic fluorinated gas, and O.sub.2, are selected to provide etched features having a substantially concave shape.



Description
BACKGROUND

The present invention relates to a process for etching substrates, and in particular, for etching dielectric layers on semiconductor substrates.

In integrated circuit fabrication, it is often desirable to etch features in an electrically insulative dielectric layer 10 on a substrate 11, as schematically illustrated in FIG. 1a. The dielectric layers 10 include for example, silicon dioxide, undoped silicate glass, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), Si.sub.3 N.sub.4, and silicon dioxide glass deposited from tetraethylorthosilane (TEOS). The dielectric layers 10 are typically used to electrically isolate devices formed on a semiconductor substrate 11, such as MOS gates formed in polysilicon underlayers 12; and can also be used to electrically isolate metal interconnect lines (typically aluminum/silicon/copper alloys) that are used to electrically connect the devices formed on the substrate (not shown).

In the etching process, a layer of photoresist is applied on the dielectric layer 10, and the photoresist layer is patterned using conventional photolithographic methods to form a patterned resist layer 14. Thereafter, conventional etching processes are used to etch features 15, such as contact holes or vias, through the exposed portions of the patterned resist layer 14. It is desirable for the dielectric etching process to provide etching selectivity ratios of greater than 10:1 with respect to the resist layer 14, and to provide etching uniformity across the substrate of less than 10%. The etching selectivity ratio is the ratio of the dielectric etch rate to the resist, or underlayer, etch rate. Etching uniformity is typically a statistical measure of the variation in size and depth of the etched features 15, across the substrate surface. After the etching process, the etched features 15 are filled with electrically conductive material 16 to form electrically conductive plugs or interconnects, which interconnect devices formed on the substrate, or interconnect lower levels of metal interconnect lines to upper levels of metal interconnect lines.