UHF ground interconnects

6617526
Add to folder: View Folders  
Keywords to Highlight:

full-text

print

pdf

permalink

Inventors

Miller, Peter A.

Application #

839151

Filed

Apr-23-2001

Published

Sep-9-2003

Current US Class

174/255
174/261
174/262
174/266
361/792
361/794
361/795

International Classes

H01R 012/04; H05K 001/11

Field of Search

174/261 174/262 174/266 174/263 174/264 174/255 361/792 361/793 361/794 361/795 361/735 361/790 361/803 439/65 257/698

Assignee

Lockheed Martin Corporation (Bethesda, MD)

Examiners

Cuneo; Kamand

Attorney, Agent or Firm

Burns, Doane, Swecker & Mathis, LLP

US Patent References

4170819   Method of making...
4211603   Multilayer circuit b...
4675788   Multi-layer circuit...
4679872   Cylindrical back pl...
5057809   Variable inductanc...
5225969   Multilayer hybrid c...
5374788   Printed wiring boar...
5376759   Multiple layer print...
5421083   Method of manufac...
5459642   Capacitor mountin...
5565262   Electrical feedthrou...
5612660   Inductance element
5808529   Printed circuit boar...
5823795   Connector between...
5847451   Multi-layered print...
5853303   Impedance and in...
5876842   Modular circuit pa...
5921815   Impedance and in...
5949030   Vias and method fo...
6019639   Impedance and in...
 

Referenced by:

View Backward References

Citation

Cite This Patent

More From Subclass 262

6411519   Package substrate
6004657   Laminated electron...
6455784   Curable sheet for ci...
5408053   Layered planar tra...
6262376   Chip carrier substr...
6879492   Hyperbga buildup...
6754057   Capacitor damage...
6274820   Electrical connectio...
6815619   Circuit board
5397861   Electrical interconn...
6831233   Chip package with...
6855625   Manufacturing met...
6239980   Multimodule interc...
5713127   Non-annular lands
6879494   Circuit package for...
5440453   Extended architect...
6198634   Electronic package...
5536908   Lead-free printed c...
4551788   Multi-chip carrier...
6271478   Multi-layer circuit...
5233135   Interconnect for inte...
5585602   Structure for provid...
5522132   Microwave surface...
6312269   Card connector cir...
6486394   Process for produci...
6512185   Printed-wiring board
5449863   Printed circuit board
4223435   Circuit board with s...
4931144   Self-aligned nonne...
6441314   Multilayered substr...
5600099   Chemically grafted...
5837886   Gas sensor
6852932   Circuit board with...
5379189   Electrical assemblies
6384347   Glass-ceramic wiri...
6617520   Circuit board
6444918   Interconnection stru...
6613986   Multilayer build-up...
6833512   Substrate board str...
5539156   Non-annular lands
6255602   Multiple layer elect...
6921867   Stress release featur...
5321211   Integrated circuit vi...
6703564   Printing wiring bo...
6074728   Multi-layered circu...
5055637   Circuit boards with...
6787708   Printed circuit boar...
6596948   Processor and pow...
4288840   Printed circuit board
6459044   Flexible multilayer...
6574116   Inverter capacitor...
4713494   Multilayer ceramic...
5276290   Electroplating proc...
5640761   Method of making...
6804881   Multilayer circuit b...
5910354   Metallurgical inter...
6078013   Clover-leaf solder...
5654528   Flexible printed cir...
6091027   Via structure
6093476   Wiring substrate ha...
5802713   Circuit board man...
5926377   Multilayer printed...
6774317   Connection compo...
6944945   Sequential build ci...
4525246   Making solderable...
6720502   Integrated circuit str...
6172305   Multilayer circuit b...
 

More From Class 174

6114624   Padmounted distri...
4769513   Splice closure system
3953663   Vacuum-heat treate...
6160219   Receptacle-mounte...
5355109   Electric noise absor...
4509820   Protective packagi...
4806402   Heat recoverable te...
4413922   Branch-off seal
6720512   Surface mount swit...
4096346   Wire and cable
4758724   Panel mounted tog...
5347091   Multilayer circuit c...
 
Abstract
A via on a printed circuit board having a circuit has a first interconnect and a second interconnect located about at least a portion of the first interconnect. The second interconnect connects to ground of the circuit and is coaxial and substantially concentric with the first interconnect and inductively coupled with the first interconnect. A method of electrically interconnecting at a via multiple layers on a printed circuit board to provide a common ground plane for a circuit is also provided. A high speed interconnection can be attained by allowing the ground return path for a circuit carried on multiple layers of a multilayer printed circuit board to remain coupled to the signal, thereby lowering ground inductance and maintaining signal integrity, even at UHF, while minimizing costs.
 
Claims
What is claimed is:

1. A via for use in a multilayer printed circuit board having a circuit, the printed circuit board including a first plurality of conductive layers and a second plurality of conductive layers, the first and second plurality of conductive layers being interleaved in a first direction which extends parallel to an axis of the via, the via comprising:

a first interconnect located about the axis of the via and electrically connecting the first plurality of interleaved conductive layers to a signal net of the circuit; and

a second interconnect having a portion located about the first interconnect for electrically connecting the second plurality of interleaved conductive layers to a ground plane of the circuit,



Description
BACKGROUND

1. Field of the Invention

The present device is directed generally to printed circuit boards. More specifically, the present invention is directed to interconnecting two or more signal layers of a multilayer printed circuit board while maintaining a well coupled signal return path to reduce signal noise.

2. Background of the Invention

Ground inductance is an industry-recognized source of ground bounce or noise. In the presence of parasitic capacitance, the ground circuit can even resonate causing extraordinary ground noise to be developed, with this effect being proportional to frequency.

Known methods are directed to minimizing ground inductance and limiting noise. Examples of various techniques may be found in U.S. Pat. No. 4,679,872, issued to Coe, and U.S. Pat. No. 5,808,529, issued to Hamre. U.S. Pat. No. 3,739,469, issued to Dougherty, Jr., the disclosure of which is hereby incorporated by reference, discloses the fabrication of a multilayered printed circuit board in which concentric through-holes (via holes) extend between layers to provide a higher density of via holes in the board. However, with increased frequencies, existing ground interconnect methods have proven inadequate and exhibit relatively high inductance. Known methods do not adequately address the need for coupling of the ground planes in a printed circuit board so as to minimize ground inductance, especially at high frequencies, such as at system clock frequencies on the order of 500 MHz or greater, or at direct frequencies on the order of 1 GHz or greater. Additionally, prior practices have become increasingly expensive and ineffective, mostly because of the incomplete coupling of the signal to the ground return path.
 
  A backplane having a layer of insulation material, a plurality of lead segments arranged in line and spaced from one another on a first surface of the...  Relates to printed circuit boards which are devoid of electrical discontinuities likely to arise in the production of two-sided circuit boards having plated-through-holes...