By forming via holes (EPO)

This disclosure is directed to a method of forming an interlevel dielectric glass layer (16) on a semiconductor device, the layer having a plurality of feed-through apertures (17--17) therein. A CW laser beam (29) is continuously raster scanned over the surface of the glass layer (16) to reflow the layer...     

An improvement in the formation of multilayer metallization systems wherein vias are formed in a dielectric insulating layer of polyimide which overlies a layer of metal such as aluminum. In accordance with the invention, the residual film remaining after oxygen plasma etching of the polyimide is efficiently...     

An improved contact hole in a method of producing a semiconductor device by forming a silicon dioxide insulating layer by a chemical vapor deposition method on a semiconductor substrate, forming a contact hole in the insulating layer diffusing phosphorus or boron impurities into a portion of the insulating...     

A process is disclosed for fabricating semiconductor devices, and especially for fabricating semiconductor devices having multiple levels of metallization separated by polyimide or other organic materials. The process avoids the sputter etching and redeposition of the lower metal layer during reactive...     

An integrated circuit processing method comprises the formation on a substrate of a metallized conductor pattern. A layer of insulating material is formed over the conductor pattern and a mask is superimposed thereon. The mask is resistant to plasma etching and is provided at predetermined positions...     

Integrated circuits wherein the width of contacts is narrowed by a sidewall oxide, so that the metal layer can be patterned to minimum geometry everywhere, and does not have to be widened where it runs over a contact.

An EEPROM fabrication process using N-well CMOS technology with a two polysilicon floating gate stack and a double layer of conductive lines providing a small reliable memory cell and high density. Channel stops and field oxide are formed by implanting boron ions, followed by a high-temperature drive-in...     

A method of forming semi-conductor devices components wherein there are at least two exposed conducting regions having passivating material overlying said regions. The passivating material is subject to etching by a given etchant. At least one, but less than all of the regions are covered with a material,...     

A photoresist layer having a prescribed pattern is formed on a substrate to be etched. The substrate is immersed into a predetermined solution to form a layer on the substrate except on those portions where the photoresist layer is formed. The photoresist layer is removed, and the substrate is etched...     

A method is provided for forming multiple layers of interconnection adjacent a planar surface. A first insulator layer is formed adjacent the selected planar surface. A first conductor layer is formed adjacent the first insulator layer. A second insulator is formed adjacent the first conductor layer....     

In the fabrication of electrodes for transistors in the BiCMOS integrated circuit, vertical windows etched in a relatively thick TEOS (or other suitable dielectric) layer, located on a relatively thin polysilicon layer, in turn located on relatively tin oxide layer areas and on relatively thick oxide...     

Contact etching is simplified by including a conformal etch stop layer underneath the interlevel or multilevel oxide (MLO). Etching through the unequal thickness of the MLO with sufficient overetching to reliably clear the thickest parts of the MLO layer will therefore not damage the silicon contact...     

A method for forming a contact in a semiconductor integrated circuit includes the formation of a conformal oxide layer over the device followed by formation of a doped glass layer. The integrated circuit is heated to cause the glass layer to reflow, improving planarity of the circuit. A second conformal...     

Two methods for wet etch removing an etch stop layer without leaving an undesired undercut are disclosed. In the first method, a reactive ion etch is stopped on an etch stop layer. The exposed etch stop is wet etch removed, leaving an undesirable undercut. The undercut is filled by chemical vapor deposition...     

A method is provided for forming multiple layers of interconnections adjacent a planar surface. A first insulator layer is formed adjacent the selected planar surface. A first conductor layer is formed adjacent the first insulator layer. A second insulator is formed adjacent the first conductor layer....     

A method of forming a contact structure comprising a first step whereby a contact hole is formed with an etching stopper film by way of self-alignment, a second step whereby the etching stopper film is removed from the contact hole, and a third step of metallization, whereby unnecessary intermediate...     

An improved semiconductor device having no posioned via produced therein includes a semiconductor substrate having a first conductor pattern formed thereon, a first insulator film provided on the semiconductor substrate to cover the first conductor pattern, and a coat applied onto the first insulator...     

A method for fabricating a semiconductor device includes steps of forming wirings on the surface of a semiconductor substrate with a plurality of diffused layers; forming a first insulating film whose surface is flattened; forming a first group of contact holes having substantially the same depth reaching...     

A technique for producing self-aligned contact openings is especially useful when the openings are to be made between conductive structures having relatively small separation. Formation of an oxide layer under particular process conditions results in a thicker layer of oxide on top of the conductive...     

A method of forming metal contact wiring layers in semiconductor devices by cleaning the surface of an exposed substrate of a contact hole formed to the SiO.sub.2 film on a semiconductor substrate with the reducing effect of N.sub.2 H.sub.4 gas, thereafter forming a TiN barrier layer by the CVD method...     

A technique for forming metal interconnect signal lines provides for planarization of an interlevel dielectric layer. A thin layer of material which can function as an etch stop, such as a metal oxide, is formed over the interlevel dielectric. An alignment process is used to pattern and define openings...     

A method of forming contact windows in an insulating layer is disclosed. The contact windows extend down to an underlying metal layer which is formed under the insulating layer. The method comprises the steps of: forming an etching mask layer having openings for defining contact window regions of the...     

A method of tapering side walls of via holes and a tapered via hole structure for an integrated circuit is provided. Via holes having steep sidewalls are provided in an insulating layer overlying a conductive layer on a substrate, with an underlying conductive layer exposed at a bottom of each via hole....     

A process for forming a contact which comprises (i) forming on a semiconductor substrate a LOCOS oxide film and a conductive pattern thereon, respectively, (ii) forming a first dielectric film and a second dielectric film on a semiconductor substrate including the LOCOS oxide film and the conductive...     

The present invention provides a programmable structure for a programmable read-only memory (PROM) which utilizes one-sided ozone spacers constructed on the digit lines as one time programmable nodes. An oxide/nitride/oxide layer (ONO) is used as an interface between underlying parallel rows of digit...     

A dry etching method whereby an SiO.sub.2 layer and an Si.sub.3 N.sub.4 layer may be etched with high selectivity for each other. As etching gas, such sulfur fluorides as S.sub.2 F.sub.2 are used which, when dissociated by electric discharges, will form SF.sub.x.sup.+ as a main etchant for the SiO.sub.2...     

The etching selectivity is controlled by appropriately changing the dimension of the opening of each contact holes in forming simultaneously a plurality of contact holes of different depth by etching. By forming a dent in advance underlying the region where a contact hole is to be formed, the depth of...     

In a method of forming contact holes in an interstage insulation layer having a thick portion on the semiconductor substrate in which a first contact hole leading to the substrate surface is to be formed and a thin portion on an electrode in which a second contact hole leading to the electrode is to...     

A structure and method for forming contact vias in integrated circuits. An interconnect layer is formed on an underlying layer in an integrated circuit. A buffer region is then formed adjacent to the interconnect layer, followed by forming an insulating layer over the integrated circuit. Preferably,...     

A method for dry etching for forming a contact hole in a silicon oxide interlayer insulating film is proposed, by which high etchrate, high selectivity, low pollution and low damage may be achieved. An etching gas containing cyclic saturated fluorocarbon compounds, such as octafluorocyclobutane (c-C.sub.4...     

Disclosed herein is a method of dry-etching SiO.sub.2 layers and Si.sub.3 N.sub.4 layers with high selectivity. The dry etching method employs a fluorocarbon (FC) gas represented by the formula C.sub.x F.sub.y (where y<x+2) in a dry-etching system capable of generating a high-density plasma having...     

A method for forming a connection between two levels in a semiconductor structure includes first forming a VIA (14) through an insulating layer (12) to an underlying structure (10). Sidewall spacers (22) and (24) are formed on the vertical walls of the VIA (14). The spacers (22) and (24) have tapered...     

A contact between a heavily-doped region in the substrate and metal is made via a hole in a thick oxide layer and a polysilicon layer. The polysilicon layer is first etched to form a hole for establishing a mask for the eventual contact hole. Prior to forming the contact hole, a sidewall spacer of polysilicon...     

A multi-layered wiring structure, having a first level metal wiring layer and a second level metal wiring layer, is formed on a semiconductor substrate. A first level interlayer insulating film which has an undulation caused by the first level metal wiring layer, a second level metal wiring layer which...     

Uniaxially conductive connector formed in situ on microchip by laser drilling an insulating layer at least 5 micrometers thick to provide holes communicating with the chip bonding sites, and depositing metal in the holes to establish electrical connection with the bonding sites. Excimer U.V. laser ablation...     

A method of forming a metal via on a semiconductor substrate having a metal layer and a dielectric layer on the metal layer, which uses an intermediate mask layer as a mask in forming the metal via instead of using a photoresist as a mask. Therefore, the spin-on glass (SOG) layer in the dielectric layer...     

A dry etching method for forming a connection opening in a insulating film of a silicon compound formed on an Al-based interconnection layer. The dry etching method consists in etching an SiO.sub.2 interlayer insulating film on an Al-1% Si layer, in a magnetic micro-wave plasma etching device capable...     

A process for forming self-aligned contact holes in a semiconductor device. In the process, a barrier layer for limiting an opened area of each contact hole is formed by use of a blanket etching process and a chemical vapor deposition process. This method eliminates the use of a mask patterning process...     

A semiconductor device with an improved contact capable of improving junction breakdown voltage and junction leakage current by forming a contact at an active region without damaging bird' beak portions of its element-isolation oxide films and a method of making this semiconductor device. The semiconductor...     

A process for producing a plurality of metallized vias in a polyimide dielectric is disclosed. The process includes depositing a polyimide precursor, then a silane and finally a metal, after patterning the polyimide and silane. The sandwich is heated to completely imidize the polyimide, crosslink the...     

A method is provided for forming a contact opening or via of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first metal region is formed over an underlying region. A first insulating layer is formed over the integrated circuit. A second insulating layer...     

A novel high performance and reliable interconnection structure for preventing via delamination. The interconnection structure of the present invention comprises a via connection which extends into and undercuts an underlying interconnection line to lock the via connection into the interconnection line.

There is disclosed a dry etching method capable of achieving the formation of vertical line patterns and the minimization of a difference in size between an isolated line pattern and an inner line pattern. When the line width of an inner line pattern is smaller than that of an isolated line pattern and...     

An MLR (multilayer resist) 3 is formed on a BPSG layer 2 on top of a silicon wafer 1, then dry etched using an etching gas 8 to form a contact hole 2a on the BPSG layer 2. Next, the polymer residues 9a and 9b adhering to the side walls of the contact hole 2a and the surface of the BPSG layer 2 are subjected...     

A method of removing material from an integrated circuit. The integrated circuit is placed within a reaction chamber, and a flow of argon and a flow of hydrogen are introduced into the reaction chamber, where the flow of hydrogen is greater than the flow of argon. The flows of argon and hydrogen are...     

According to this invention, an etching stopper film constituted by a silicon nitride film is stacked on an insulating film constituted by a silicon oxide film for protecting a wiring to prevent damage to the wiring caused by anisotropic dry etching for forming a contact hole. A resist pattern having...     

A trench isolation region (32) is fabricated to include a trench liner (28) comprised of aluminum nitride. The aluminum nitride trench liner is useful in borderless contact applications wherein a contact opening (56) is etched in an interlayer dielectric (54) and overlies both an active region. (e.g....     

A semiconductor memory device includes, a) a semiconductor substrate; b) a field effect transistor gate positioned outwardly of the semiconductor substrate; c) opposing active areas formed within the semiconductor substrate on opposing sides of the gate; d) a capacitor electrically connected with one...     

A method of forming a tunnel-free tungsten plug is described. Semiconductor device structures are provided in and on a semiconductor substrate. An insulating layer of borophospho-tetraethoxysilane (BP-TEOS) is deposited overlying the semiconductor device structures. Contact openings are etched through...     

A method is provided for filling undesired sublithographic contact hole defects in a semiconductor structure caused by misalignment and undesirable overlap of metal line images over contact openings during photolithographic patterning. Unwanted contact between conductive metallization levels through...     

After an interconnection layer such as Al alloy is formed on an insulating film covering the surface of a substrate, a connection hole is formed through a laminate of the insulating film and the interconnection layer at the area corresponding to the region to be connected. An adhesion layer such as TiN...     

A method of forming a metal line structure for use with a semiconductor device includes the steps of: preparing a semiconductor substrate; forming a first line on the semiconductor substrate; forming a plug pattern on the first line; forming at least one insulating layer on an exposed surface of the...     

After an insulating film is deposited over metal patterns, a resist film is coated over the whole surface of the insulating film until the surface of the resist film becomes flat. The resist film is removed by reactive ion etching until a partial surface area of the insulating film deposited over the...     

The present invention discloses a method of fabricating a multi-level interconnection on semiconductor substrate. A dielectric layer is formed on the substrate, and a first conductive layer is formed on the dielectric layer. An IMD layer is formed on the first conductive layer, a buffer layer is formed...     

A hydronic radiant heater bed warmer (RBW) is mounted in the support structure beneath the top surface of a conventional bed that has a mattress on springs supported by the bed support structure. The RBW includes: a source of heated supply water; a supply water line from the source; a return water line...     

According to this invention, an etching stopper film constituted by a silicon nitride film is stacked on an insulating film constituted by a silicon oxide film for protecting a wiring to prevent damage to the wiring caused by anisotropic dry etching for forming a contact hole. A resist pattern having...     

After a resist mask is selectivity formed on an upper portion of a gate electrode containing mainly aluminum. At this state an anodization process is performed using an electrolytic solution, to form an anodic oxide film in a region other than a region of the upper portion on which the resist mask is...     

An improved semiconductor device fabrication method capable of improving the insulation characteristic between neighboring electrodes, which includes the steps of a first step which coats a conductive material on an active region of a semiconductor substrate having an active region and a non-active region...     

A (method using a composition) for removing resists and etching residue from substrates containing at least one nucleophilic amine compound having oxidation and reduction potentials, at least one organic solvent, water and, optionally, a chelating agent. The chelating agent is preferred to be included...     

An improved method of forming a tunnel-free tungsten plug is described. Semiconductor device structures are provided in and on a semiconductor substrate. An insulating layer of borophospho-tetraethoxysilane (BP-TEOS) is deposited overlying the semiconductor device structures. Contact openings are etched...     

The present invention provides a method for manufacturing a semiconductor device, including a step of forming an opening 1 such as a contact hole and a succeeding heat treatment step such as contact annealing, wherein the heat treatment is performed upon completion of filling the opening with a diffusion-preventing...     

A semiconductor device is manufactured in accordance with the procedure as follows. At first, there is formed an interlayer insulating film including a SOG film (3) overlying a first metal wiring (1), a thin silicon nitride film (10) overlying the SOG film (3) and an oxide film (4) overlying the silicon...     

An improved etching procedure that uses three processing steps to vastly improve HAR opening profile and improved under-layer selectivity. A new three sequence etching process is provided during which a new three-gas plasma etch is to be used. This new etching sequence is preceded by a new main etch...     

There is provided a dry etching method which does not contribute to earth anathermal due to the green house effect and which has a good etching characteristics. According to the present invention, the flow rates of Ar, O.sub.2, and C.sub.3 F.sub.6 supplied from gas sources 152, 154 and 156 are regulated...     

A semiconductor device is made up of a substrate having a top surface, and a fin type capacitor having a first electrode including a first part which extends upwards from the substrate and a second part which extends approximately parallel to the top surface of the substrate from the first part. The...     

A contact hole forming method uses a negative resist film having an absorptivity of 0.5 .mu.m.sup.-1 or above to suppress standing-wave effect in forming contact holes in a silicon dioxide film or the like underlying the negative resist film by anisotropic etching. The contact hole forming method comprises...     

A method is provided for filling undesired sublithographic contact hole defects in a semiconductor structure caused by misalignment and undesirable overlap of metal line images over contact openings during photolithographic patterning. Unwanted contact between conductive metallization levels through...     

A method of making vias in a semiconductor IC device having adequate contact to the surface of the interconnects and without inadequate landing is disclosed. The method has interconnects formed in a metal layer on the substrate of the IC device, and a first dielectric layer is formed covering the surface...     

A method of forming a viahole in an interlayer insulating film without the formation of irregularities on a side wall of the viahole. The method includes a first step of forming a viahole in an interlayer insulating film having a multi-layer structure of plural kinds of insulating layers; a second step...     

A method of forming a via. A substrate having a first conductive layer thereon is provided. An inter-metal dielectric layer is formed over the substrate layer by high density plasma chemical vapor deposition. An etch stop layer is formed on the inter-metal dielectric layer. An oxide layer is formed on...     

An underlying Al alloy wiring 3 and an inter-layer insulation film 4 are formed sequentially on a semiconductor substrate 1 via an inter-layer insulation film 2. An inter-layer insulation film 5 highly hygroscopic and containing much moisture is made and etched back to flush depressions by the underlying...     

A method of creating a rerouting pattern on a semiconductor die or cube by providing a semiconductor die having an active surface with bond pads thereon and sides. A layer of electrically insulating material is sputtered over the active surface and the sides while exposing the bond pads. Electrically...     

A method of forming a connection hole, which includes the steps of: laminating an etching stopper film made of a SiN based material and an interlayer insulating film made of a SiOx based material on a substrate in this order; forming an organic film pattern on the interlayer insulating film on the basis...     

A method of forming a dual damascene structure includes forming an oxide layer and a mask layer there on, which both have protuberances over the conductive layers. Then a chemical mechanical polishing is performed to remove the protuberances and to form openings. The protuberances are above the conductive...     

A method for cleaning polymer film residues from in-process integrated circuit devices is disclosed. Specifically, a method for forming a contact via in an integrated circuit is disclosed in which the formation of a metallization conductive element is exposed through a dry anisotropic etch. During the...     

The photolithographic etching of contact holes in trenches in an insulator layer over a silicon body is improved by adjusting properly the depth of the trench and the thickness of the photoresist used in the photolithography.

A method for etching of sub-quarter micron openings in insulative layers for contacts and vias is described. The method uses high resolution DUV photolithography. By using a thin layer of photoresist to pattern a hardmask, full advantage of the high resolution can be attained. The hardmask in turn, is...     

A method of manufacturing interconnects disclosed in the invention comprises the following steps. First, a substrate having an insulator formed thereon is provided. A first dielectric layer having a first conductive section and a second conductive section formed therein, is formed on the insulator. A...     

A method of forming wirings which includes forming a film of a silicon-containing metal layer at a high temperature on an underlying metal, thereby forming a silicon alloy layer which includes the underlying metal and the silicon-containing metal during film formation. In a case of forming wirings by...     

The present invention intends to form multilayer interconnects without deteriorating the advantage of an organosiloxane film (an interlayer dielectric), i.e., the low dielectric constant. According to the present invention, an organosiloxane film, a silicon nitride film, an inorganic SOG film, and a...     

A method for forming a borderless, contact or via hole, has been developed, in which a thin silicon nitride layer is used as an etch stop to prevent attack of an underlying interlevel dielectric layer, during the opening of the borderless, contact or via hole, in an overlying, interlevel dielectric layer....     

A method for forming a plurality of self-aligned via holes applied to a semiconductor device is disclosed. The method includes steps of (a) providing a substrate forming thereon a conducting layer forming thereon a sacrificial layer; (b) partially removing the sacrificial layer while retaining a plurality...     

An etching method used in the high density plasma etching system to etch a silicon oxide dielectric layer to form openings of different depths. The method uses a mixture of C.sub.4 H.sub.8, CH.sub.2 F.sub.2, and Ar as an etching gas source to etch the silicon oxide dielectric layer, forming a plurality...     

A semiconductor device structure and method for producing a shaped etch-front during an etching process. In one embodiment, the present invention is comprised of a first layer of material which is disposed above a contact layer. In this embodiment, the first layer of material has a first etch rate. Next,...     

A high-selectivity via etching process. The process includes the steps of: forming an etchstop layer 840 of a material selected from the group consisting of Ti--Al, Ti--Al--N, Ta--Al, Al--N, Ti--Al/Ti--N, Ti--Al--N/Ti--N, Ta--Al/Ti--N, and Ti--Al/Ti--Al--N; forming a dielectric layer over the etchstop...     

A trench-isolated active device and a method of forming a trench-isolated active device on a semiconductor substrate wherein the conductive layer of the device is self-aligned with an isolation trench is disclosed. The method includes applying a conductive layer over a dielectric layer (e.g., gate oxide),...     

A method of fabricating a semiconductor device is disclosed for connecting a bit line to a semiconductor substrate in a self-aligned fashion in non-contacting relation to a word line and precluding a crystal defect in the semiconductor substrate which might induce a leakage current. An isolation insulative...     

A method for fabricating a via that uses a hard etching mask for etching the via. A photoresist layer used to pattern the hard etching mask is removed before starting the via etching. The hard etching mask includes a TiN etching mask, a silicon nitride etching mask, and a oxide/TiN etching mask. For...     

A composite dielectric layer and method of forming the composite dielectric layer for the passivation of exposed copper in a copper damascene structure are described. The composite layer consists of a passivation dielectric layer and an etch stop dielectric layer and is formed over the exposed copper...     

A method for forming a semiconductor device includes providing a semiconductor body having source and drain regions therein and a gate electrode on a portion of a surface of such body between the source and drain regions. A dielectric layer is provided on the surface of the semiconductor body over the...     

The invention concerns a method of forming a layer of metal on a substrate and fill the via with high throughput. A layer of metal can be formed on a substrate using sequentially a cold deposition step, a slow hot deposition step and a rapid hot deposition step. The cold deposition step need only be...     

An integrated circuit includes a metallization layer (30). A first layer (14) is formed outwardly from a semiconductor substrate (10). Contact vias (16) are formed through the first layer (14) to the semiconductor substrate (10). A second layer (20) is formed outwardly from the first layer (14). Portions...     

A method for preventing a contact plug on a semiconductor substrate from being poisoned. A part of the metal layer with a large and flat surface region is removed to result in a plurality of metal layers with smaller surface areas on the substrate. A first dielectric layer is formed on the metal layers....     

The present invention provides for an improved method of creating vias and trenches during microchip fabrication. According to the invention, the vias and trenches are self-aligned during the photolithography process by using two layers of specially selected resists and exposing the resists such that...     

Etching residue is selectively removed employing a substantially non-aqueous composition containing a fluoride containing compound and certain organic solvents. Preferred compositions also include an anhydride.

A first resist film for EB exposure, a buffer film, and a second resist film for i-line exposure are applied sequentially onto a substrate. Thereafter, the second resist film and the buffer film are subjected to patterning for forming a first opening. Then, dry etching is performed with respect to the...     

A method for improving the damascene process window for metallization utilizes an anti-reflective coating to increase the precision of the photolithography process. An inter-layer dielectric and an anti-reflective layer are formed in turn on a semiconductor substrate. The inter-layer dielectric is patterned...     

This is a method of forming mechanically robust vias and entrenched conductors on a dielectric layer (which dielectric layer is on an electronic microcircuit substrate which vias and entrenched conductors are electrically connected to a conductive area on the surface of the substrate) and a structure...     

A method is provided for forming an unlanded via hole that substantially solves both the problems of high resistance and via profile loss due to etching. A patterned conductor layer on a first dielectric layer is provided firstly. A first insulating layer is then formed on the first dielectric layer...     

A semiconductor device, in which wiring layers are electrically isolated from each other by an insulating film which includes an amorphous carbon fluoride film insulating film containing carbon and fluorine as main components and the wiring layers are electrically connected to each other by a conductive...