Hermetically sealed semiconductor ceramic package

5406120
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Inventors

Jones, Robert M.

Application #

093456

Filed

Jul-19-1993

Published

Apr-11-1995

Current US Class

257/698
257/701
257/703
257/704
257/706
257/707
257/712
257/774
257/E23.101
361/712
361/714

International Classes

H01L 023/02; H05K 007/20

Field of Search

257/762 257/700 257/705 257/696 257/698 257/706 257/701 257/703 257/704 257/707 257/712 257/713 257/718 257/719 257/720 257/723 257/734 257/774 361/601 361/676 361/688 361/690 361/704 361/707 361/709 361/711 361/712 361/717 361/718 361/719 361/713 361/714

Examiners

James; Andrew J.

Attorney, Agent or Firm

Barlow & Barlow, Ltd.

US Patent References

4172261   Semiconductor dev...
4922324   Semiconductor inte...

Referenced by:

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Citation

Cite This Patent

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Abstract
A ceramic hermetic package is provided having conductive material bonded into apertures in the ceramic housing that connect with a die mounted on a thin substrate through wire and pad connections. The substrate has a heat sink affixed to the bottom and electrical connections are formed on the opposite face of the package from the heat sink so that the encased semiconductor may be mounted on circuit boards in either a vertical position or in a position where the heat sink is horizontal but facing upward.
 
Claims
I claim:

1. A hermetic package for housing a power semiconductor comprising:

(a) a ceramic substrate having a planar upper surface and at least a side edge with said power semiconductor disposed on said planar upper surface;

(b) a continuous ceramic wall rising from said side edge to form a cavity; said wall defining a top planar surface;

(c) at least two lead apertures in said wall between the top planar surface and the upper surface of the substrate; said lead apertures extending from said top planar surface to said upper surface of the substrate in a direction perpendicular to said top planar surface;

(d) electrically conductive material in said lead apertures between the top planar surface of the wall and the upper surface of the substrate electrically connected to said power semiconductor; said electrically conductive material extending from the top planar surface of the wall through the wall to the upper surface of the substrate thereby providing exposed portions of said electrically conductive material; said exposed portions having a surface substantially co-planar with said top planar surface of the wall;



Description
BACKGROUND OF THE INVENTION

This invention relates generally to an electronic or semiconductor device package structure and, more particularly, a package for a semiconductor device as a hermetically sealed unit.

Semiconductor devices employed in high current type applications, commonly referred to as power devices, generate a substantial amount of heat in operation of the device. In the past it has been very common to have a package known as a TO-3 package, which essentially had a large heat sink area, the die being encapsulated by a metal cap, while the leads were brought out through metal-to-glass seals. If demand calls for a package which must be electrically isolated, a ceramic substrate has to be placed in the package and, if the package was a power package and had to dissipate heat, the ceramic substrate would generally be beryllium oxide, and in order to help to dissipate the heat, that is spread it, an efficient means must be provided in contact with the substrate. Whatever this means may be, it must not stress the substrate by differences in thermal expansion coefficients. The commercial acceptability, therefore, of such devices is based upon their ability to dissipate the generated heat at a high rate as excessive heat retention can destroy the semiconductor die within the device.
 
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