Soldering with resilient contacts

5615824
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Inventors

Fjelstad, Joseph
DiStefano, Thomas H.
Smith, John W.

Application #

410324

Filed

Mar-24-1995

Published

Apr-1-1997

Current US Class

029/840
029/860
228/180.1
257/E23.067
257/E23.069
257/E23.078

International Classes

B23K 001/00

Field of Search

228/180.1 228/180.21 29/593 29/840 29/860

Assignee

Tessera, Inc. (San Jose, CA)

Examiners

Elkins; Gary E.

Attorney, Agent or Firm

Lerner, David, Littenberg, Krumholz & Mentlik

US Patent References

3937386   Flip chip cartridge...
3998377   Method of and app...
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4597617   Pressure interconn...
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4695870   Inverted chip carrier
4696096   Reworking method...
4716049   Compressive pedest...
4783719   Test connector for el...
4818728   Method of making...
4821947   Fluxless applicatio...
4846704   Test socket with imp...
4887760   Bonding sheet for e...
4893172   Connecting structur...
4902606   Compressive pedest...
4913336   Method of tape bon...
4924353   Connector system fo...
4937006   Method and appar...
4950173   Service temperatur...
4950623   Method of building...
4975079   Connector assembl...
5006792   Flip-chip test socket...
5006917   Thermocompressio...
5046953   Method and appar...
5046957   Solder plate assem...
5048746   Tunnel for fluxless...
5053922   Demountable tape-...
5057969   Thin film electronic...
5086337   Connecting structur...
5092034   Soldering intercon...
5115964   Method for bondin...
5123850   Non-destructive bur...
5131852   Electrical socket
5133495   Method of bonding...
5152695   Surface mount elec...
5154341   Noncollapsing mul...
5173055   Area array connector
5181859   Electrical connector...
5196726   Substrate for packa...
5203075   Method of bonding...
5207585   Thin interface pelli...
5228861   High density electri...
5261155   Method for bondin...
5261593   Direct application o...
5281684   Solder bumping of...
5282565   Solder bump interc...
5328087   Thermally and ele...
5346118   Surface mount sold...
5349495   System for securing...
5349500   Direct application o...
5354205   Electrical connectio...
5417362   Electrical connecti...
5489750   Method of mountin...
 

Referenced by:

View Backward References

Other References

Design News, Jan. 17, 1994, "Tiny Filter Quashes EMI". Electronic buyers' News, Issue 867, Aug. 16, 1993, "Quieting Connectors Down" by David Gabel. TRW Data Technologies 1994 Brochure. 1994 ITAP & Flip Chip Proceedings, "A Tab Tape-Based Bare Chip Test and Burn-In Carrier", Nolan et al (pp. 73-179). 1994 ITAP & Flip Chip Proceedings, "Mechanical Interconnection System For Solder Bump Dice", Hill et al, (pp. 82-86). Multichip Module Technologies and Alternatives: The Basics, Alan D. Knight, (pp. 504-509; 521-523). IEEE Transaction on Components, Packaging and Manufacturing Technology, Part A, vol. 18, No. 2, Jun. 1995, "Constriction Resistance of Microcone-Based Contacts". "Supplementary Interconnection Devices", Ginsberg et al, Multichip Modules & Related Technologies, (pp. 201-229).

Citation

Cite This Patent

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Abstract
A method of making a solder connection. An element bearing a solder mass is forcibly engaged with another element bearing a resilient metallic contact so that the contact wipes the surface of the solder mass and so that the contact is deformed and bears against the wiped surface. While the contact is in its deformed condition, the contact and solder mass are brought to an elevated bonding temperature sufficient to soften the solder, so that the contact penetrates into the solder mass under the influence of its own resilience. The contact bonds with the pure solder inside the solder mass, so that the effective bonding can be achieved even without flux.
 
Claims
What is claimed is:

1. A method of making an electrical connection comprising the steps of:

(a) forcibly engaging a first element bearing a mass of a bonding material and a second element bearing a resilient metallic contact so that said contact wipes the surface of said bonding material mass and so that said contact is deformed and bears against the wiped surface; and

(b) bringing the contact and the bonding material mass to an elevated bonding temperature sufficient to soften the bonding material, so that the contact penetrates into the solder mass under the influence of its own resilience; and

(c) cooling the engaged contact and mass.

2. A method as claimed in claim 1 wherein said step of bringing the contact and the mass to said elevated bonding temperature is performed by heating the contact and mass after said engaging step.



Description
BACKGROUND OF THE INVENTION

The present invention relates to soldered connections for microelectronic devices such as semiconductor chips and the associated circuit panels, and to methods of making and using such connections.

Microelectronic circuits require numerous connections between elements. For example, a semiconductor chip may be connected to a small circuit panel or substrate, whereas the substrate may in turn be connected to a larger circuit panel. The chip to substrate or "first level" interconnection requires a large number of individual electrical input and output ("IO") as well as power and ground connections. As chips have become progressively more complex, the number of I/O connections per chip has grown so that hundreds of connections or more may be needed for a single chip. To provide a compact assembly, all of these connections must be made within a relatively small area, desirably an area about the area of the chip itself. Thus, the connections must be densely packed, preferably in an array of contacts on a regular grid, commonly referred to as a "Bump Grid Array" or "BGA". The preferred center-to-center distance between contacts or "contact pitch" for chip mountings is on the order of 1.5 mm or less, and in some cases as small as 0.5 mm. These contact pitches are expected to decrease further. Likewise, chip mounting substrates and other circuit panels used in microelectronics have become progressively more miniaturized, with progressively greater numbers of electrical conductors per unit area. Connectors for these miniaturized panel structures desirably also have very small contact pitch. Connections of chip mounting substrates to other elements are referred to as "second-level" interconnections.
 
  In a soldering process leads of components on a circuit board are dipped into a solder bath to solder them to the underside of the board. The board is...