Memory testing

A large scale integrated (LSI) chip or semiconductor device includes a memory array and associated logic circuitry. The array is "embedded" in the sense that it is not directly accessible, either in whole or in part, from the input and output terminals or pads of the device. To facilitate testing there...     

An LSI semiconductor device includes a memory array incorporating address and data registers, and associated combinatorial and or sequential logic circuitry. The array is "embedded" in the sense that the memory array is not directly accessible, either in whole or in part, from the input and output terminals...     

A diagnostic system is disclosed for detecting malfunctions in the access circuitry utilized to control the reading, writing, and refreshing of a plurality of semiconductor memory modules. More specifically, a pair of access circuits are provided for each module with each access circuit only controlling...     

An apparatus for enabling a central processing unit (CPU) to directly read the address transferred to a memory module to permit the CPU to test the address circuitry of the memory module without actually referencing an addressable location of the memory array within the memory module. A status register...     

A testing apparatus, having an address generator for providing address signals to a test device and to a reference device, is provided with a programmable mask for passing only selected least significant X and Y address bits to the reference device.

A test pattern generator is used for generating a series of address signals such as for exercising an integrated circuit memory. Master reference clock means are used to trigger a three stage counting circuit and also a circuit array of exclusive OR gates. The outputs of the stages of the counter provide...     

Apparatus consisting of combinations of interconnected logic elements for generating preselected sequences of addresses for the listing of a matrix memory as a function of preset constants and variable timing impulses, wherein there are first and second X and Y address generators with controlled selection...     

A memory system includes an integrated circuit comprising a plurality of testably interconnectable cells in a tessellation on a semiconducting wafer. A controller for acting as an interface between the wafer and some host system is coupled to the wafer via a port formed by the omission of one of the...     

A byte-wide memory with column redundancy. The redundant columns can each be substituted for any column in the half-array, without regard to which bit position the defective column relates to. Fuses store the address information of the defective columns, and when a match between the externally received...     

An associative memory used to translate a virtual page number (VPN) of a virtual word address to a physical page number (PPN) of a physical word address of a random access memory of a digital computer system is provided with a pair of independently addressable validity bit arrays, each of which arrays...     

A memory device in accordance with the invention has an array of memory cells including a plurality of main memory cells which are adapted to be utilized by a user for storing information and a plurality of checking memory cells which store data placed therein at the time of manufacturing of the array...     

A semiconductor tester in which an address is generated by a test pattern generator in synchronism with an operating clock from a timing generator, the address is applied to a memory under test, and a check is made to determine if the power source current to the memory under test is larger than a predetermined...     

Test circuitry is included in a PROM memory for detecting shorts between bit lines and word lines and shorts or leaks in a memory cell. The circuitry enables a selected positive voltage to be applied across all memory cells in the memory so that the existence of leaky memory cells or shorts in the memory...     

In a one-chip microcomputer, a EPROM is formed together with a ROM and RAM on one semiconductor substrate. Data such as fixed data necessary in the microcomputer can be changed by the use of the EPROM. In case data are to be written in the EPROM, a EPROM writer is used. This EPROM writer outputs write...     

A semiconductor memory device is comprised of memory cells arranged in a matrix fashion; defective row line detect circuits for producing logic "1" when a defective row line is selectd to which a detective cell is connected; defective column line detect circuits for producing a logical "1" signal when...     

A tester of circuit devices is disclosed which uses commercially available component parts but is capable of high performance testing of hierarchical memory cards requiring data pulses of variable pulse widths at high repetition rates. The tester includes two memories connected to respective shift registers...     

An integrated semiconductor memory includes n identical memory cell fields each having a data width equal to m, n.multidot.m data lines for writing-in and reading-out memory data into and out of the memory cell fields, m first data separators for applying the memory data as a function of addressing data...     

Integrated semiconductor memory includes n identical memory cell fields, each having a data width equal to m, n . m data lines for writing-in and reading-out memory data into and out of the memory cell fields, m first data separators each having an assigned data input terminal for applying the memory...     

Very large dynamic RAM integrated circuits are rendered self-testing by using on-chip generation of data test patterns with very high fault coverage, and concurrent testing of storage cell subarrays to reduce overall testing time. A test generator, which may operate in combination with the refresh control...     

A memory test pattern generator generates a memory test pattern by reading out data from a microinstruction program memory according to an instruction of an address counter and causing an address generator, a data generator and a timing generator to generate an address, data and a timing signal, respectively,...     

A memory access control apparatus has a plurality of request reception sections, respectively connected to a plurality of units for supplying requests, for receiving a block read request from the corresponding units, and dividing the block read request into a plurality of read requests and outputting...     

In an EEPROM capable of writing data in a page mode, an output portion of a Y decoder is provided with a column latch circuit for storing a Y gate line selected by a Y decoder at the time of writing data. The column latch circuit activates the Y gate line selected in response to the stored information...     

An electrically programmable ROM is provided for avoiding frauds by producing, internally in the memory, the different potentials which it uses for verifying the memory points chosen. The verification of writing of information in a point is obtained by subjecting this point to a calibrated selection...     

A CN.sup.2 memory testing circuit for generating a sequence of C(N.sup.2 +1) memory addresses which will accomplish a CN.sup.2 test with the least possible memory transitions. In one embodiment for an odd integer C, the mth bit in the memory address sequence comprises at least one repetition of a unique...     

A microprocessor that detects and corrects random soft errors during program execution occurring in its storage elements (memory). Such a microprocessor utilizes a bit serial architecture and single error correction double error detection techniques that automatically detect and correct soft errors occurring...     

For sufficient diagnostic operation, there is disclosed a semiconductor memory device having a write-in mode, a read-out mode and a diagnostic mode. The seminconductor memory device includes: (a) a check-bit producing circuit operative to produce check-bits based on data bits of a piece of data information...     

A random access memory including address error checking. The random access memory includes an address decoder that activates data cells from among the plurality of data cells in the memory. The random access memory also includes an address encoder that supplies an address determined by the data cells...     

A semiconductor storage device is disclosed which has a plurality of common data lines for delivering information from plural memory cells selected out of a plurality of memory cells during a normal operation mode, a plurality of amplifier circuits provided corresponding to the plurality of common data...     

A semiconductor memory device is disclosed, in which a word line address translation unit, a data line address translation unit, a first spare memory and a second spare memory are provided in addition to a main memory to relieve a defective memory cell in the main memory. Spare word line address signals...     

A memory management unit is capable of judging that a specific bit has been partially rewritten by checking it against a dummy bit stored in a tag memory which is included in the memory management unit and thus correcting a parity bit. Accordingly, it is possible to accurately execute a parity check...     

A DRAM test system includes a storage location tester and controller tester. The storage location tester utilizes an error correction code which generates redundancy symbols corresponding to inverted data that are the binary inverse or compliment of the redundancy symbols corresponding to the non-inverted...     

A semiconductor memory device is provided which includes a plurality of data lines coupled to memory cells and to a detecting arrangement for detecting if logical levels of each of the data lines coincide to each other or not. A test read arrangement is also provided which stores the same information,...     

In a multibit test mode for a dynamic RAM, a plurality of complementary data lines are simultaneously connected to the complementary common data lines and the levels of noninversion signal lines and inversion signal lines of the complementary common data lines are compared with a predetermined reference...     

A circuit for testing signatures at a pin in a CMOS device where this device is operable when it is powered by a voltage within the predetermined range. During the test mode, a task voltage whose magnitude is below that of any voltage in the operating range as applied so that parasitic diode turn-on...     

A semiconductor integrated circuit device comprising a first circuit forming a random logic and outputting a plurality of first parallel data of plural bits, a second circuit which receives the plurality of first parallel data and supplies a plurality of second parallel data of plural bits to the first...     

A memory system storing data detects and corrects an error in the stored data. The memory device includes a coding circuit for generating a systematic code including a data word and an error checking and correcting (ECC) code when the data word is supplied from a data bus during data writing, a memory...     

In a memory tester in which data read out of an address of a memory under test, specified by a pattern generator, is compared with an expected value and the result of comparison is written into a failure analysis memory at the address corresponding to that of the memory under test from which the data...     

An information processing device includes a random access memory storing parallel program data, a counter generating a first address supplied to the random access memory and a second address, and a selector for converting the parallel program data read out from the random access memory in accordance...     

An abort circuit for a microprocessor includes a circuit receiving and latching an external abort signal to produce an internal abort signal, and circuitry responsive to the internal abort signal for preventing register transfer circuitry from responding to register transfer signals during execution...     

A memory device for use with an external apparatus having a predetermined function is removably attached to the apparatus and comprises a connection portion for electrically removably connecting the memory device to the external apparatus; a memory portion for storing information supplied from the external...     

A data pattern generator in which the address generation of a program counter (11) is controlled in accordance with an operation code and an operand read out of an instruction memory (12'). An address/data pattern is generated in response to an address/data computing instruction read out of the instruction...     

A configurable device uses a plurality of parallel units which are made up of cells for storing individual bits of information. These cells are identified by address signals and selected to be interrogated. The selected cells are interrogated to determine information stored therein and a signal is produced...     

An offline redundancy memory test system replaces fail memory equipment, under the control of a test system CPU, with fail memory equipment under the control of a second CPU. The second CPU is dedicated to the analysis of the contents of the offline redundancy memory test system fail memory, for redundancy...     

A method for testing and comparing the access times of disk drives in a real time system containing a multiplicity of likes drives. The method includes the steps of generating random locations for each of the drives to access, initializing each of the drives to a common position, determining the time...     

A circuit for carrying out ordinary "write" and "read" operation during operation of applying a test voltage to a cell opposite electrode in test operation is provided. The circuit converts a test mode instruction signal to an ordinary operation instruction signal in a semiconductor memory device. The...     

A method for performing background disk sector analysis for drives, including drives dedicated to redundancy and/or fault recovery techniques, in an intelligent, microprocessor based disk array. The method directs the microprocessor to wait a specified time and test for disk activity. In the absence...     

In a memory tester for testing memories of the type having a polarity inversion feature there are provided a bit select circuit for selecting from an address generated by an address generator a plurality of bits necessary for a logical expression expressing a polarity-inverted data storage area of the...     

A self-test that is variable to test an SRAM that is embedded on a semiconductor die is achieved. The self-test is performed by a modular self-test circuitry that can be varied to permit generating addresses, and data patterns for various SRAM architectures and sizes. An address block develops addresses...     

A memory fault mapping apparatus detects faults generated in a memory array during on-line operation. As the memory array is randomly accessed, single bit error are detected, corrected, and mapped into an error memory. The errors may be mapped in an error memory having a memory location for each memory...     

A semiconductor memory device having: a RAM port for randomly accessing a memory cell array having memory cells disposed in matrix; a SAM port for serially accessing data of one row of the memory cell array; a mode switching unit for switching the operation mode of the SAM port between an ordinary data...     

A plurality of redundant rows/columns are added to a semiconductor memory array wherein each redundant row/column is located at a predetermined location in the memory array so as to divide the memory into equal sectors. Switches are utilized to connect the memory columns and rows and redundant memory...     

A memory testing assembly (50) for testing a memory device under test ("DUT") includes a row address converter (58) and a column address converter (62). The row and column address converters translate generic row and column count signals into correct row and column address signals that address desired...     

An IC memory testing apparatus comprises a pattern generating circuit, a decision circuit, a first-in memory circuit which stores the defect data of a IC memory under test and simultaneously reads the resulting data. A latch circuit is also used to shorten the testing time. The resulting information...     

An error ratio detector according to the present invention, which detects the error ratio of error correction-coded data with a syndrome, reduces the error pulse occurrence probability by using only the errors in an M (<N) period within each block (of N bits) as errors for calculating the error ratio,...     

A data output control circuit of a semiconductor memory device. The data output control circuit comprises an input signal detector for detecting a desired signal, a controller for selecting one of a plurality of data output buffers and a data output controller for driving the selected data output buffer....     

An apparatus and method for improving the testability of six cell CMOS SRAM circuits. The technique involves adding transistors and the ability to effectively disable the precharge circuitry during the test mode. This makes the pull up transistors the only current source for switching the memory cell....     

A state tracer system comprising a counter for counting the time taken until, upon receipt of a first request signal from a storage unit, an error takes place; an A-register within which the count number A of this counter is set and its state is held; an X-register which allows the time taken to reach...     

A testing circuit for reading and writing a greater number of data bits in parallel during a single clock cycle than through I/O data pins in a memory device. The testing circuit comprises at least one data-in buffer, a plurality of write buffers coupled to the data-in buffer, a plurality of write buses...     

A semiconductor device comprises a plurality of circuits formed on an IC chip area, having electric power systems each being independent, a plurality of power potential supply wires connected to the plurality of circuits, respectively, a plurality of power potential supply terminals connected to the...     

A semiconductor integrated circuit device includes an external connection terminal receiving a normal signal varying between a high potential and a low potential, and a test mode setting signal, an input circuit which is connected to the external connection terminal and receives the normal signal via...     

A data writing/reading device of a camera, in case it has become impossible to write data correctly to certain memory area of an E.sup.2 PROM because of frequent rewritings, can write data to other memory areas of the E.sup.2 PROM, and read out the data. Write requiring data to the E.sup.2 PROM is written...     

A semiconductor memory comprises a memory cell (20) array in which memory cells (M) are placed at the intersections of word lines (WL1 to WLM) and bit lines (BL1 to BLn), a bit line select circuit (21) coupled with the bit lines (BL1 to BLn) for selecting the bit lines, a potential supply circuit (22)...     

A fault tolerant memory system including a plurality of memory chips arranged to produce an array of addressable locations. Each addressable location has a plurality of data bits and a plurality of check bits for checking the integrity of all the data bits and check bits at a given addressable location....     

A communication device connected to a packet network, which is provided with a storage portion having communication-tracing-information storing areas respectively assigned to logical channels and a communication processing portion for identifying a logical channel by a network header of transmission...     

To carry out a transparent test of integrated circuits, all of the state registers and input/output registers that determine the applications' execution context are included into circular scan paths having the output of the last stage connected to the input of the first stage. Before the test, the contents...     

A method for comprehensively testing embedded RAM devices and a means for detecting if any of the cells within the embedded RAM devices have a slow write recovery time. The preferred mode of the present invention utilizes built-in self-test (BIST) techniques for testing the embedded RAM's within a VLSI...     

An address pattern generator for generating regular addresses in a freely set aside area of the memory cell to be tested. The arrangement of the column address generator is structured the same as that of the row address generator wherein both the column address generator and the row address generator...     

An IC element testing device includes a test pattern generating unit for generating test patterns, a power supply unit for generating a power supply voltage, a superposed voltage generating unit for generating a superposed voltage, and a superposing unit for superposing the superposed voltage on the...     

A response stack validation checking circuit for providing a hardware based approach for monitoring the integrity of a read and a write pointer in a memory stack. The present invention may be utilized in systems having a common memory controller for controlling the read and write pointers or a system...     

A dynamic random access memory device includes a plurality of dynamic memory cells. Each dynamic memory cell is formed at least in part by a cell plate which is connected to a normally fixed reference voltage. The reference voltage is produced by a cell plate generator. The cell plate generator has a...     

In an electrically erasable programmable ROM in which written data contains in a very limited part high-frequency reload data, the memory capacity is reduced in the following new way. An address detecting circuit (12) detects whether or not designated write addresses are within a predetermined range...     

The present invention, provides a single BIST which can test various memories of different sizes, types and characteristics by using a state machine to select and generate all patterns required for testing all of the memories on the chip, and impressing all of the data, including expected data, and address...     

In one aspect, a memory device employing device-level error correction tracks the status of the error correction in terms of whether error correction is active or inactive, whether an uncorrectable error beyond the capability of the device-level correction is detected, whether a recovery option from...     

A flash memory testing apparatus is capable of testing a flash memory while maintaining the conventional memory test functions. The flash memory testing apparatus obtains the number of programming pulses applied to each address of the flash memory. The flash memory testing apparatus executes the following...     

Powerfail durable non-volatile random access memory (NVRAM) testing is provided by using the available NVRAM itself to remember its own state of testing, by sequencing through the testing process, and by carefully placing memory image checksums within the NVRAM. The correctness of the NVRAM image is...     

In computers, a test of memory is generally performed at the time of powering up. In one form of the invention, this type of test is run on part of Random Access Memory (RAM), while allowing data or a program to reside in another part. Then, after the partial test is completed, the data is transferred...     

A self-diagnostic device for checking the performance of memory matrix in semiconductor devices is presented. The device is applicable particularly to those IC testers having high bit and high capacity memories. The device is capable of performing march and checker tasks simultaneously. The program data...     

A method of testing synchronous dynamic random access memories (SDRAMs) having a pair of memory banks, comprised of writing data into a first of the pair of memory banks at a first clock speed that can be used by a tester, transferring the data at a second clock speed much higher than the first clock...     

The disclosure pertains to a memory redundancy circuit. A main memory may, if there should be defective zones (defective columns for example), be replaced by a redundancy memory. A defective address memory is initialized during the testing of the main memory. During normal operation relating to access...     

A failure analyzer for the semiconductor tester which tests a plurality of devices at the same time and stores a first fail information for each device under test (DUT) and inhibits further fail information from being stored in a fail memory. The failure analyzer includes a plurality of comparators connected...     

A semiconductor device capable of inspecting itself efficiently. Output data from a circuit under test is supplied to a testing data-generating circuit and a non-periodic function transformation is performed so that testing data generated by the testing data generating circuit has a pseudo-random pattern....     

It is an object to reduce circuit scale and increase operation speed of a memory test circuit which performs a memory test according to the ping-pong pattern. An address signal of a remarked cell is generated by an LFSR (76) and address signals for other cells are generated by an LFSR (75). The LFSR...     

A high speed pattern generator is disclosed that can generate a test pattern at high speed for an electronics device to be tested, such as a flash memory where the test flow varies depending on the test results. The pattern generator includes an address generator for generating address data of the test...     

A system measures the positions of bit errors in digital recording devices and displays the physical locations of the bit errors and their distribution in such a manner that they can be grasped visually and intuitively. The system compares a data stream to be measured with a correct data stream and measures...     

It is an object to provide a test circuit which properly finds faults of memory cells of a storage circuit. Registers XB1, 0, YB1, 0 of a circuit SGC1 supply address data which includes four order all cycle sequence. A generating portion 10a provides "1" when data XB1, 0 are "10" and provides "0" in...     

An error allowing pattern matching circuit comprises a data conversion circuit which converts receive data transmitted serially thereto from an input terminal into parallel data and outputs the parallel data, a ROM to which the parallel data from the data conversion circuit are inputted as an address...     

A scan latch is described which comprises a capture half-latch, a release half-latch and an update half-latch. The capture half-latch has an input terminal connected to receive an input signal, a control terminal connected to a clock signal, and an output terminal. The release half-latch and update half...     

The memory control this invention includes a microprogram-read-only-memory (CROM) containing micro-instructions for operation of an integrated-circuit memory, a program counter multiplexer (PCM) to select instructions from the control-read-only-memory, a micro-instruction decoder with BILBO control (MID/BC),...     

Powerfail durable non-volatile random access memory (NVRAM) testing is provided by using the available NVRAM itself to remember its own state of testing, by sequencing through the testing process, and by carefully placing memory image checksums within the NVRAM. The correctness of the NVRAM image is...     

Waveforms are acquired from a DUT into segments corresponding respectively to vectors of a vector pattern repetitively applied to the DUT. The waveform segments are displayed relative to vector numbers of the pattern to facilitate comparison of stimulus/response, debug, and other tasks. The relationship...     

Two data storage systems are interconnected by a data link for remote mirroring of data. Each volume of data is configured as local, primary in a remotely mirrored volume pair, or secondary in a remotely mirrored volume pair. Normally, a host computer directly accesses either a local or a primary volume,...     

A semiconductor memory device includes: a plurality of sectioned memory arrays; a comparing circuit; and a predetermined terminal, and configured so that the test mode, the same test data is written in simultaneously into a plurality of memory arrays, and when the written data is read out, the data is...     

A redundancy implementation circuit has a set of memory cells each storing an address bit of an address identifying a redundant memory location and a set of comparator circuits each connected to compare the address bit stored in a memory cell with an incoming address bit. A switch selectively connects...     

A semiconductor test system facilitates failure analysis of memory devices by being able to switch one situation where expected data used for an address fail memory is the same as data showing charge/discharge states in the memory cells of a memory device under test and another situation where the expected...     

An integrated circuit includes a circuit architecture that enhances the I.sub.DDQ testability of circuitry such as random access memories. Increased accuracy and test speed are achieved by partitioning the circuit array into multiple partitions. Pairs of partitions connected to a voltage source node...     

A data processing system has at least one processing module containing one or more blocks of memory, having control registers which are accessible via a diagnostic interface, and a clock module which distributes system clocks to the processing module(s), the operation of which is controllable using a...     

A test program producing device including a test item information producing unit for reading circuit information, macro to be tested information and a library to produce necessary information regarding test items for an LSI to be examined, a test possibility/impossibility determining unit for calculating...     

A method of testing a first memory such as a RAM having data storage at a plurality of individually addressable storage locations is provided. A portion of the address for the addressable locations of the first memory is supplied as an output from a second memory such as a CAM. The second memory includes...     

A semiconductor integrated device is disclosed which is capable of selectively executing a memory test and a logic test. The device includes a logic part for realizing a plurality of operation functions in logic, a memory part having a given integration and for storing data, a pad part including a pad...     

A process and implementing system is provided for conducting a memory test for isolating and identifying failed cache memory modules in a memory subsystem of a computer system. The methodology initially selects 303 a block of memory which is twice the size of the cache 105 being tested. The cache 105...