Fabrication system and fabrication method

Disclosed is a fabricating system including a plurality of processing apparatuses connected to each other by means of an inter-apparatus transporter, wherein one group of semiconductor wafers are processed in processing apparatuses and other group of wafers are transported to specified processing apparatuses for a time interval from (To+T) to a time To; and another group of wafers are processed and the remaining group of wafers are transported for a time interval from (To+T) to (To+2T). Since processing apparatuses can receive at least one of works from the inter-apparatus transporter for a time interval T min, the distribution of works from the transporter to processing apparatuses is completed for the time interval T min. The transporter is emptied for each time interval T min, and works are unloaded to the emptied transporter, which makes easy the scheduling, control and management of the transporting of a plurality of works in the fabricating system. Moreover, since the fabricating system including processing apparatuses is periodically controlled at a cycle time T min, the scheduling of a plurality of works can be made easy, to enhance the level of optimization, thus improving the productivity.

 

What is claimed is:

1. A method of fabricating semiconductor devices comprising processing semiconductor wafers by repeatedly using a plurality of processing apparatuses each having a plurality of processing chambers, the processing having synchronized timing of individual processes including loading, unloading and transporting times of the semiconductor wafers.

2. A method of fabricating semiconductor devices comprising processing semiconductor wafers by repeatedly using in pipeline mode a plurality of processing apparatuses, each of the processing apparatuses having a plurality of processing chambers and having substantially a same processing time period including loading, unloading and transporting times of the semiconductor wafers.

3. A method of fabricating semiconductor devices comprising processing a semiconductor wafer by repeatedly using a plurality of processing apparatuses each having a plurality of processing chambers, coupled with a transporting apparatus for transporting the semiconductor wafer between each processing apparatus having a substantially same processing time period as the transporting time period of the transporting apparatus.

4. A method of producing semiconductor devices comprising a first step of processing a semiconductor wafer by using a first processing apparatus having a plurality of processing chambers, and a second step of processing another semiconductor wafer by using a second processing apparatus having a plurality of processing chambers, wherein said second step is synchronized with said first step.

5. A method of producing semiconductor devices according to claim 4, wherein said first step performs depositing of a metal film on a main surface of said semiconductor wafer in said first processing apparatus, and said second step performs depositing of an insulator film on the main surface of said other semiconductor wafer in said second processing apparatus.

6. A method of producing semiconductor devices according to claim 5, wherein said first step includes the step of stocking said semiconductor wafer in a first stocking chamber, and said second step includes the step of stocking said other semiconductor wafer in a second stocking chamber.

7. A method of producing semiconductor devices according to claim 5, wherein said chambers in said first processing apparatus comprises a stocking chamber, a preparing chamber, a transporting chamber, a pretreatment chamber, a sputtering chamber and unloading chamber; said chambers in said second processing apparatus comprises a film deposition chamber, a stocking chamber, a preparing chamber, a transporting chamber, and an unloading chamber.

8. A method of producing semiconductor devices according to claim 4, wherein said first step is for depositing a metal film on the main surface of said semiconductor wafer in said first processing apparatus, and said second step is for lithography processing continued to said first step.

9. A method of fabricating semiconductor devices comprising processing semiconductor wafers by repeatedly using a plurality of processing apparatuses each having a plurality of processing chambers, the processing having synchronized timing of individual processes.

BACKGROUND OF THE INVENTION

The present invention relates to a fabrication system and a fabrication method capable of fabricating various kinds of semiconductor devices for a short period of time.

In automated fabricating plants, various kinds of works are processed in a plurality of automated fabrication apparatuses. In such a fabricating plant, the scheduling of processing is determined in terms of the appointed data of works, working efficiency, and the minimized amount of semi-finished products between processing apparatuses. To smoothly perform the above processing in the automated fabricating plant, it is important to enhance the reliability of each processing apparatus and a system managing computer; and it is more important to enhance the function of managing the whole fabricating system. This is because, in the automated fabricating plant, the fabricating system is automatically operated, and it is managed by the unit having the function of managing the fabricating system.

In particular, in a fabricating plant for semiconductor devices, a plurality of semiconductor wafers of various kinds are processed using a plurality of processing apparatuses according to processing steps and processing conditions determined for every kinds of wafers. In some cases, the same apparatus is used for different processes, and thereby the repeating of the processing becomes very complicated. Accordingly, a high management function is required for the fabricating system for semiconductor devices. One example of the complicated processing in the fabricating system for semiconductor devices will be described. A circuit element used in assembly of a semiconductor device is formed of at least one semiconductor chip. In general, the chips are obtained by cutting circuit element areas arranged on a semiconductor wafer in the longitudinal and lateral directions, along the boundaries. Various processing steps are required to form circuit element areas on a semiconductor wafer. For example, processes of forming areas including the desired impurities atoms on a semiconductor wafer includes (1) a process of cleaning the wafer; (2) a heat treatment process of oxidizing the surface of the wafer; (3) a resist coating process of coating a photoresist on an oxide film and drying it; (4) an exposing process of exposing the desired area of a resist by an energy particle beam such as a light beam, electron beam or X-ray; (5) a developing process of selectively removing the exposed or non-exposed portion of the photoresist; (6) an etching process of removing the exposed oxide film using the resist partially remaining on the oxide film as a mask; (7) a resist removing process of removing the resist partially remaining on the oxide film; (8) an impurities introducing process of depositing impurities on the wafer or allowing them to permeate a surface layer portion by exposing the wafer in the impurity atmosphere using the oxide film as a mask, or using CVD, vapor-deposition or ion implantation; and diffusing the impurities up to the desired depth by heating; and (9) an etching process of removing the unnecessary oxide film or the like on the surface of the wafer. A sequence of processes from the resist removing process (3) to the developing process (5) or to a resist baking process applied after the developing process as needed are called photolithography processes, and which are repeatedly used for the formation of the circuit element. Namely, the photolithgraphy processes are used for the formation of a metal film and the formation of a passivation layer, other than the formation of the impurity introducing area. In this way, various processes are applied to the wafer, and further, some processes, for example included in the photolithography processes are repeatedly applied to the same semiconductor wafer by twice or more. In general, the number and order of various processes applied to the wafer are partially different for the kinds of products. In processing of semiconductor wafers, several hundreds of kinds of works are processed by one method selected from several tens of methods. Moreover, the number of semiconductor wafers processed simultaneously are extremely large. It is extremely difficult to process these semiconductor wafers under good management. As a result, there occur problems in that the appointed date is made longer, and the working ratio of each processing apparatus is reduced thereby lowering the number of products finished per unit time. Moreover, the cleanliness of a clean space in which semiconductor wafers are processed must be usually kept to be high. However, since many operators get around in a clean space in which processing apparatuses are disposed, dust adhering on the clothes of the operators and floors are scattered, which makes it difficult to keep the high cleanliness of the clean space. This causes a disadvantage that the dust adheres on semiconductor wafers thereby reducing the percent non-defective. To cope with this disadvantage, there has been known a method, exemplified in Japanese Patent Laid-open No. SHO 64-6540, wherein works are processed in an unmanned system for preventing the contamination of semiconductor wafers, and a sequence of processing steps are organically controlled to manage a plurality of semiconductor wafers of various kinds, thereby reducing the term of works, enhancing the percent non-defective, and lowering the number of operators.

The prior art managing system for automating the very complicated fabricating system for semiconductor devices described above has been described, for example in "Operation of LSI Production System to Reduce Development Investment and to Meet Diversified Needs" (Nikkei Microdevice, August, 1992, pp. 66-74). At the beginning of the automated fabrication, a centralized control system has been extensively performed, in which processing information in a plant is all inputted in a central computer and the work indications are performed by the computer. In this system, when the centralized control computer is normally operated, it usually grasps the whole state of the fabricating system, and thereby a high level control can be realized. However, this system is disadvantageous in that when the computer fails, the control of the fabricating system is stopped because of the absence of any means replaced with the computer. A software incorporated in the centralized control computer is of a model type including processing apparatuses and transporters, and many cases, algolizm depending on the features of processing apparatuses and transporters is incorporated therein. Accordingly, in renewal of a processing apparatus, the software incorporated in the computer must be exceedingly corrected, thus requiring a large amount of labor for the correction and expansion of the software. A distributed processing system is used to solve the above disadvantage of the centralized control system, in which the centralized computer is replaced by a plurality of computers. The management of the distributed processing system is described, for example in Japanese Patent Laid-open No. SHO 63-244730. However, even when either of the above-described managing systems is used to automate the fabricating system, the effect of shortening the term of works and the effect of increasing the number of products per unit time by enhancing the working ratio and the percent non-defective do not reach the sufficient level for achieving the suitable time/suitable amount production.

The first reason for this is that in the prior art, the transporting between a plurality of processing apparatuses is performed by a batch system, in which the so-called "lot" constituted of a plurality of semiconductor wafers is taken as a unit. The diameter of a semiconductor wafer has been enlarged for enhancing the productivity. For the purpose of performing a high accurate processing to such a semiconductor wafer, the processing in each processing apparatus has been changed from the conventional batch system to a single wafer processing. However, even in the single wafer processing apparatus, so long as semiconductor wafers are processed for each unit of lot, one processing takes a time required to process the number of semiconductor wafers constituting one lot, which makes longer the waiting time until the subsequent processing. Therefore, even if the management of products and processes is enhanced using computers, there is a limitation to the shortage of the term of works in principle. Moreover, the waiting time between specified two continued processes is greatly dependent on the lot, that is, on the semiconductor wafer, thus obstructing the improvement in percent non-defective.

The second reason for this is that, it is very difficult to optimize a plurality of complicated processes even by the control using computers in the lot processing environment, thus reducing the productivity. In a fabricating system, the number of processing apparatuses capable of performing the same process is determined on the basis of the throughput while examining the processing number for each wafer in each processing apparatus, and thus the processing ability (wafer/unit time) of each processing apparatus is equalized. However, in some cases, the fabricating system cannot actually achieve the processing ability thus calculated as a whole. Namely, it is impossible to optimize the complicated processes, the balance in the processing amount in each processing apparatus is not kept, thus reducing the productivity.

The third reason for this is that, in the fabricating system by batch transporting, a large amount of works in process (non-finished products) are required to ensure the productivity, thereby making longer the term of works. Moreover, when the term of works is made longer, the stay time of semiconductor wafers in a clean space where the fabricating system is contained is made longer, and thereby a high cleanliness of the clean space is required to prevent the reduction of percent non-defective. The fine pattern of a circuit element requires a high cleanliness, and it becomes difficult to realize a clean space with a high cleanliness, because the buildings having the clean space becomes very complicated and expensive, and a large energy is required to keep the clean space. One of the disadvantage of the prior art fabricating system by the batch transporting is to require a clean space with a high cleanliness.

To cope with the above disadvantage, in recent years, a fabricating system using a single wafer transporting has been proposed, for example in Japanese Patent Nos. HEI 4-130618 and HEI 4-199709, wherein a single wafer is transported between a plurality of processing apparatuses The prior art fabricating system disclosed in Japanese Patent Laid-open No. HEI 4-199709 has a disadvantage in increasing the number of processing apparatuses. Even when a plurality of processes can be performed using the same processing apparatus, a plurality of processing apparatuses must be prepared in the order of the processing steps. If not so, the flows of semiconductor wafers are crossed to each other, and two or more wafers cannot be simultaneously processed in the fabricating system. As described above, for example, the photolithography processes are repeatedly used for the formation of a circuit element. The resist coating and resist baking process included in the photolithography processes is repeatedly applied to the same semiconductor wafer by twice or more. To prevent an increase in the number of processing apparatuses, the processing apparatus required in some processes must be commonly used. To commonly use the resist coating and baking process, the resist coating and resist baking apparatus must be directly connected to all of processing apparatuses for performing processes before and after the resist coating and resist baking process by means of an inter-apparatus single wafer transporter not by way of other processing apparatuses. For example, it must be connected to all of the film deposition apparatuses. It is impossible to realize such a construction by the system shown in Japanese Patent Laid-open No. HEI 4-199709.

On the contrary, in the system shown in Japanese Patent Laid-open No. HEI 4-130618, all of processing apparatuses are connected to each other by means of an inter-apparatus single wafer transporter, so that the above-described disadvantages can be solved. This is because each semiconductor wafer can be transported between any two processing apparatuses. The disadvantage of this system lies in that a plurality of semiconductor wafers are crossed to each other in processing apparatuses and transporters. Only by connecting single wafer processing apparatuses to each other by means of a single wafer transporter, it cannot be achieved to obtain a high efficiency in simultaneously processing a plurality of semiconductor wafers.

First, it is required to determine the number of processing apparatuses on the basis of the throughput while examining the processing number for each semiconductor wafer in each processing apparatus, and to equalize the processing ability (wafers/unit time) of each process. In the system shown in Japanese Patent Laid-open No. HEI 4-130618, the number of processing apparatuses is determined on the basis of a failure frequency and a repairing time, and the first processing for one wafer is completed and then the next wafer is loaded in the first processing apparatus, with a result that wafers are stayed in the processing apparatus with a lowest processing ability. To avoid the above problem, the processed amount must be reduced on the basis of the ability of the processing apparatus, which causes a disadvantage that the term of works is shortened and the wafer output is reduced. It is necessary to examine the transporter and the transporting time. In the single wafer transporting, the transporting is performed for each unit of a single wafer, so that it becomes very complicated. In the system shown in Japanese Patent Laid-open No. HEI 4-130618, the crossing of semiconductor wafers in the transporting stage is not examined. The control and management for single wafer processing and single wager transporting are also complicated, and is very difficult to be satisfactorily realized.

In the prior art systems described in Japanese Patent Laid-open Nos. HEI 4-130618 and HEI 4-199709, all of processing apparatuses are of a single wafer processing type; however, by adopting the single wafer processing for all processes, the productivity is reduced in terms of the existing throughput. The above-described prior art systems fail to examine this point, which is one reason why these systems are not extensively used.

The prior art managing system has the following problems. In either of the centralized control system and the distributed processing system, the management of the prior art fabricating system is based on a unit of the so-called lot constituted of several to 25 pieces of wafers. In this case, wafers constituting a lot are contained in a cassette case, so that the management of information for each lot can be performed by the addition of an IC card to each cassette case. The reason why such an auxiliary means is required is as follows: namely, the information to be managed in the system is large; and further, in the case that the management of information is all dependent on a computer for managing the information of the whole system, when there occurs the malfunction and system-down of the information managing computer, all of the management information in the fabricating system is lost, resulting in a large damage. In the fabricating system of the distributed processing system described in the above document "Operation of LSI Production System to Reduce Development Investment and to Meet Versified Needs" (Nikkei Microdeviec, August, 1992), an IC card is attached to each lot. A method of utilizing an identification symbol of a cassette case is disclosed, for example in Japanese Patent No. SHO 61-128512. However, as described above, a processing apparatus of the batch type has been gradually changed into that of the single wafer processing type. Moreover, the transporting between processing apparatuses has been changed from the batch type to the single wafer type. To make efficient use of the advantage of the inter-apparatus single wafer transporting which is at least partially used in the fabricating system, the management of information for each semiconductor wafer is at least partially inevitable. In the inter-apparatus transporting where wafers are transported in a manner not to be contained in a cassette case, an auxiliary storing means such as the IC card moved together with wafers having wafer information to be managed cannot be used. Moreover, since the renewing number of processing information necessary for processing in each processing apparatus becomes extremely larger than in the batch transporting, which causes a problem in that the management of information by the auxiliary storing means such as the IC card is large in the renewal frequency and is cannot be used. To cope with this problem, a method in which information on the kind and process is held in a semiconductor wafer itself is described in Japanese Patent Laid-open Nos. SHO 57-157518, SHO 58-50728, SHO 63-288009, HEI 2-292810 and HEI 5-83520. A method in which information is written in a chip is described in Japanese Patent Laid-open No. SHO 60-10641. In either method, the technique is limited only to the writing or reading of information, and it does not examine the management of information contained in a fabricating system. Since the number of the transporting between processing apparatuses becomes extremely larger, the management of information in the inter-apparatus transporter is required to be managed. In view of the foregoing, there have been required a fabricating system for semiconductor devices which is suitable for single wafer management and is capable of solving the above-described problems; and a fabricating method using the system. Moreover, there have been required a fabricating system for semiconductor devices capable of optimizing a plurality of complicated processing steps controlled by computers, improving the productivity, and reducing the term of works, in the environment of the above-described management of information of a single wafer; and a fabricating method using the system.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a fabricating system capable of shortening the term of a sequence of processes applied to works, making efficient use of processing apparatuses for enhancing the productivity while improving the percent non-defective thereby enlarging the number of products finished per unit time, and eliminating a clean space with a high cleanliness conventionally required; and a fabricating method using the system, which are particularly suitable for a semiconductor fabricating system and a fabricating method using the system mainly performed by single wafer processing and transporting.

The above object can be achieved, according to the present invention, by provision of a fabricating system including:

at least two processing apparatuses; and

L sets (L: positive integer) of inter-apparatus transporters;

wherein either of the processing apparatuses or either of a plurality of the processing apparatuses having the same processing function includes:

a means for receiving and stocking at least one set of works from either of the inter-apparatus transporters for a time interval T min (T: positive integer) after a time To; and

a means for processing a set of works received before the time To, and unloading a set of already-processed works to either of the inter-apparatus transporters at a time (To+N.times.T) (N: positive number).

The above inter-apparatus transporter for connecting at least two of the above processing apparatuses capable of applying continued processes to each other, preferably, includes a means for transporting a set of works between the two processing apparatuses for a transporting time of L.times.T min or less not by way of other processing apparatuses.

The above transporter preferably includes a means for transporting and stocking a set of works started to be unloaded from a processing apparatus at a time (To+N.times.T) to and in another processing apparatus capable of applying a continued process until a time (To+(N+L).times.T).

Moreover, the above object can be achieved, according to the present invention, by provision of a fabricating system capable of applying the steps of:

applying the m-th process to the n-th set of works (n, m: positive integer) for a period from (n+2.times.m-3).times.T min to (n+2.times.m-2).times.T min on the basis of a time To;

performing the transporting by an inter-apparatus transporter from the processing apparatus in which the m-th process is performed to a processing apparatus in which the (m+1)-th process is performed for a time interval from (n+2.times.m-2).times.T min to (n+2.times.m-1+L).times.T min; and

applying the (m+1)-th process to the n-th set of works for a time interval from (n+2.times.m-1+L).times.T min to (n+2.times.m+L).times.T min.

In the above fabricating system, preferably, all of processing apparatuses for applying continued processes to sets of works are connected to each other by means of inter-apparatus transporters, and all of processing steps applied to a plurality of sets of works are performed by a pipe-line processing method.

In the above fabricating system, preferably, the transporting between processing apparatuses is automated, and works are transported in a partially clean space filled with nitrogen or in vacuum.

As for the managing system, according to the present invention, there is provided a fabricating system wherein a plurality of computers manage the managing information of process progress, and scheduling information of processing and transporting reflected by the result of the scheduling of processing and transporting for semiconductor wafers contained in the system.

Preferably, the above information is generally managed by a computer provided in the fabricating system, and is further managed by each computer distributed in each or set of processing apparatuses and transporters.

The scheduling of processing and transporting is preferably determined by the computer for generally managing the above information and the computer distributed in each or set of the processing apparatuses and the transporters.

Preferably, the above managing information of process progress and the above scheduling information of processing and transporting are for each semiconductor wafer.

These and other objects and many of the attendant advantages of the invention will be readily appreciated as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawing.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a plan view showing one example of a fabricating system for semiconductor devices according to the present invention;

FIG. 2 is a plan view showing one example of a metal film deposition apparatus constituting the fabricating system according to the present invention;

FIG. 3 is a diagram showing one example of a processing procedure for semiconductor wafers in the metal film deposition apparatus shown in FIG. 2;

FIG. 4 is a diagram showing one example of a processing procedure for a plurality of semiconductor wafers in the fabricating system according to the present invention;

FIG. 5 is a plan view showing one example of an insulator film deposition apparatus constituting the fabricating system according to the present invention;

FIG. 6 is a diagram showing a processing procedure for semiconductor wafers in the insulator film deposition apparatus shown in FIG. 5;

FIG. 7 is a plan view showing one example of a lithography apparatus constituting the fabricating system according to the present invention;

FIG. 8 is a diagram showing a processing procedure for semiconductor wafers in the lithography apparatus shown in FIG. 7;

FIG. 9 is a plan view showing one example of a metal film dry etching apparatus constituting the fabricating system according to the present invention;

FIG. 10 is a diagram showing a processing procedure for semiconductor wafers in the dry etching apparatus shown in FIG. 9;

FIG. 11 is a plan view showing one example of an insulator film dry etching apparatus constituting the fabricating system according to the present invention;

FIG. 12 is a view showing a processing procedure for semiconductor wafers in the dry etching apparatus shown in FIG. 11;

FIG. 13 is a plan view showing another example of the fabricating system according to the present invention;

FIG. 14 is a diagram showing a procedure for sequentially processing a plurality of semiconductor wafers using the lithography apparatus;

FIG. 15 is a diagram showing a procedure for sequentially processing a plurality of semiconductor wafers using the metal film dry etching apparatus;

FIG. 16 is a diagram showing a procedure for sequentially processing a plurality of semiconductor wafers using the insulator film dry etching apparatus;

FIG. 17 is a plan view showing one example of an insulator film deposition apparatus constituting the fabricating system according to the present invention;

FIG. 18 is a diagram showing a procedure for sequentially processing a plurality of semiconductor wafers using a metal film deposition apparatus;

FIG. 19 is a diagram showing a procedure for sequentially processing a plurality of semiconductor wafers using a cleaning apparatus;

FIG. 20 is a graph showing the relationship between a processing time and a wafer output in metallization processes using the inventive system and old system;

FIG. 21 is a plan view showing a further example of the fabricating system for semiconductor devices according to the present invention;

FIG. 22 a graph showing the relationship between a processing time and a wafer output in metallization processes using the inventive system and old system;

FIG. 23 is a plan view showing a further example of the fabricating system for semiconductor devices according to the present invention;

FIG. 24 is a perspective view showing a further example of the fabricating system for semiconductor wafers according to the present invention;

FIG. 25 is a graph showing the relationship between a continued processing ratio and a processing time;

FIG. 26 is a diagram showing the flow of applying two continued processes to two works using the inventive system and old system;

FIG. 27 is a plan view showing a further example of the fabricating system for semiconductor devices according to the present invention;

FIG. 28 is a plan view showing one example of a metal film deposition apparatus constituting the fabricating system according to the present invention;

FIG. 29 is a diagram showing a processing procedure for semiconductor wafers in the metal film deposition apparatus shown in FIG. 28;

FIG. 30 is a diagram showing one example of a processing procedure for a plurality of semiconductor wafers in the fabricating system according to the present invention;

FIG. 31 is a view showing one example of a processing procedure for a plurality of semiconductor wafers in the fabricating system according to the present invention;

FIG. 32 is a plan view showing one example of an insulator film deposition apparatus constituting the fabricating system according to the present invention;

FIG. 33 is a view showing a processing procedure for semiconductor wafers in the insulator film deposition apparatus shown in FIG. 32;

FIG. 34 is plan view showing one example of a lithography apparatus constituting the fabricating system according to the present invention;

FIG. 35 is a diagram showing a processing procedure for semiconductor wafers in the lithography apparatus shown in FIG. 34;

FIG. 36 is a plan view showing one example of a metal film dry etching apparatus constituting the fabricating system of the present invention;

FIG. 37 is a diagram showing a processing procedure for semiconductor wafers in the dry etching apparatus shown in FIG. 36;

FIG. 38 is a view showing one example of an insulator film dry etching apparatus constituting the fabricating system of the present invention;

FIG. 39 is a diagram showing a processing procedure for semiconductor wafers in the dry etching apparatus shown in FIG. 38;

FIG. 40 is a plan view showing a further example of the fabricating system for semiconductor wafers according to the present invention;

FIG. 41 is a graph showing the relationship between a processing time and a wafer output in metallization processes using the inventive system and old system;

FIG. 42 is a view showing the construction of a fabricating system of the present invention;

FIG. 43 is a view showing one example of a data base contained in a memory;

FIG. 44 is a view showing another example of a data base contained in a memory;

FIGS. 45 and 46 are views for explaining the relationship between the inventive system and the data base;

FIG. 47 is a graph showing the relationship between a processing time and a wafer output in metallization processes using the inventive system and old system;

FIG. 48 is a view for explaining the relationship between the inventive system and the data base;

FIG. 49 is a view for explaining the shifting of wafer information in a memory; and

FIG. 50 is a plan view showing one example of an inter-apparatus transporter according to the present invention.

DETAILED DESCRIPTION OF THE INVENTION

In a fabricating system of the present invention, any processing apparatus can receive and stock at least one set of works from either of L pieces of inter-apparatus transporters for a time interval T (min) after a time To. The distribution of sets of works from the inter-apparatus transporters to the processing apparatuses is performed for a time interval L.times.T min. One of L pieces of transporters is perfectly emptied until a time (To+L.times.T). Sets of works are started to be unloaded from some processing apparatuses to the emptied inter-apparatus transporter after the time (To+L.times.T), and are then distributed to the processing apparatuses again until a time (To+2L.times.T). Thus, sets of works are sequentially unloaded to L pieces of the inter-apparatuses, one of the inter-apparatus transporters can be emptied for each time interval T min. By making empty one of the inter-apparatus transporters for each time interval T min, and unloading set of works to the emptied transporter, it becomes possible to make easy the scheduling, control and management of loading and unloading of sets of works between processing apparatuses and inter-apparatus transporters. This makes it easy the scheduling, control and management of transporting of a plurality of sets of works in a fabricating system, to enhance the level of the optimization, thus improving the productivity. Each processing apparatus only receives or unloads a set of works from or to either of the inter-apparatus transporters for each time of T min. With this construction, the fabricating system including the processing apparatuses is periodically controlled with the cycle time T min, so that the scheduling for processing a plurality of sets of works is made easy, resulting in the improved productivity. Namely, according to the inventive system, the scheduling, control and management of the processing and transporting, and further the whole production management are made extremely easy, to enhance the level of the optimization, thus improving the productivity.

To reduce the term of works, a set of works started to be unloaded from each processing apparatus to one of L pieces of the transporters at a time (To+T) are preferably those distributed and stocked in the processing apparatus from a time interval from (To-L.times.T) to the time To, and are processed until a time (To+T). However, in a processing apparatus in which the processing for a set of works takes a time T min or more, the above requirement is not necessarily satisfied. Namely, a set of the works distributed in the processing apparatus before a time (To-L.times.T) and are processed for a time interval T min or more may be unloaded to one of the transporters at a time (To+T). For example, even the batch type processing apparatus in which a set of works (M pieces or more) are processed once may satisfy the necessary function for the processing apparatus of the present invention by the addition of the stocking function or the function of loading/unloading a set of works (M pieces or more) between the processing apparatus and the inter-apparatus transporter with a cycle time T min.

A plurality of sets of processing apparatuses having the same function may satisfy the necessary function for the processing apparatus described above. For example, when two processing apparatuses in each of which the processing is performed for a time interval more than T min and less than 2T are periodically controlled with a cycle time 2T while shifting the starting time by T min, a set of processing apparatuses have the same function as that of the processing apparatus in which the processing is controlled with a cycle time less than T min, that is, the function of receiving and stocking a set of works from the inter-apparatus for a time interval T min after To, and unloading at least one set of works from the processing apparatus to the inter-apparatus after a time (To+T).

In the continued processing to a plurality of sets of works, sets of works are not necessarily unloaded from all of the processing apparatuses to the transporters for each time interval T min. In some cases, the unloading is not performed from a processing apparatus in which a set of works to be processed are not distributed. Moreover, when sets of works in the number exceeding the number of the processing apparatuses having the same function are distributed in the processing apparatuses, sets of the works are overlapped. At this time, a means for stocking a plurality of sets of works may be provided in each processing apparatus, or a stocking apparatus for stocking a plurality of sets of works may be separately provided in the fabricating system.

The inventive system is effective to shorten the term of works. The term of works is reduced by a pipeline processing, other than the effect of enhancing the productivity. The pipeline process is suitable for applying a plurality of processes to a plurality of sets of works. In the pipeline processing of the inventive system, a plurality of continued processes are combined with the transporting therebetween. In this pipeline processing, a time interval L.times.T min is allocated to the transporting. The pipeline processing is effective to process and transport a plurality of works, and is most effective to process and transport one work as a unit (M=1).

As described above, semiconductor wafers used as in the semiconductor industry have various kinds, and they are subjected to a large number of various processes. Consequently, the number of sets of works is increased. As the number of processes is increased, the pipe line processes achieves the effect of reducing the term of works, and is most effective, when L=1.

The pipeline processing of the present invention is effective to reduce the term of works compared with the conventional lot processing. This will be described with reference to FIG. 26, wherein L=1 and M=1. In FIG. 26, two of continued processes (a) and (b) are applied to two works (A) and (B). In the pipeline processing, the work (A) is transported directly after being subjected to the process (a) by the single wafer transporting manner, and is subjected to the process (b). The work (B) is subjected to the process (a) after the processing of the work (A) in the process (a) is completed, and is transported by the single wafer transporting manner like the work (A) and is subjected to the process (b). When each of the processes (a) and (b), and the transporting takes a time interval T min for each work, a time required to complete all processing and to finally transport the work (B) is 5T min. In the lot processing, after the works (A) and (B) are subjected to the process (a), they are transported, and are subjected to the process (b). When the transporting in this case takes a time interval T min, a time required to perform all processing and to finally transport the works (A) and (B) is 6T min. The pipeline processing reduces the total time by T min. As the numbers of works and processes are increased, the difference between the pipeline processing and the lot processing becomes increased.

In the inventive system, the transporting between processing apparatuses is automated, and works can be transported in a local clean space filled with nitrogen or in vacuum, thus eliminating the clean space with a high cleanliness.

The fabricating system has a data base for generally managing the managing information of process progress for each semiconductor wafer, and also a plurality of data bases each containing part of the above general managing data base, so that when the general managing data base is broken by any cause and contains erroneous information, the fabrication can be continued on the basis of the data contained the other data bases. On the contrary, when a plurality of the data bases are broken an contain erroneous information, the fabrication can be continued on the basis of the general managing data base. When the above data base has the information on result of processing and transporting reflected by the result of processing and transporting, it may be used for the feedforward control to enhance the accuracy of the processing. When the above data base has the scheduling information of processing and transporting reflected by the scheduling of processing and transporting, it may be used to determine the operational condition of the processing and the transporting by computers distributed in each or set of the processing apparatuses and inter-apparatus transporters.

When the present invention is applied to a fabricating system and a fabricating method for semiconductor devices in which the single wafer processing and single wafer transporting are performed, it is possible to perform the single wafer information management with a high reliability, and to make efficient use of the single wafer transporting. Namely, it is possible to shorten the term of a sequence of processes applied to semiconductor wafers, to improve the productivity and percent non-defective thereby increasing the number of products finished for unit time, and to eliminate the clean space with a high cleanliness.

The present invention will be more clearly understood with reference to the following examples.

In addition, in the following description, numeral 101 designates an inter-apparatus single wafer transporter; 102 is a metal film deposition apparatus; 103 is an insulator film deposition apparatus; 104 is a lithography apparatus; 105 is a stocking apparatus; 106 is a metal film dry etching apparatus; 107 is an insulator film dry etching apparatus; and 108 is a loading/unloading apparatus. Numerals 201 and 202 are lithography apparatuses; 203 and 204 are dry etching apparatuses; 205 and 206 are film deposition apparatuses; 207 is a cleaning apparatus; 208 is a looped transporter; 209 is an interface; and 210 is as stocking apparatus. Numerals 301 and 302 are lithography apparatuses; 303 and 304 are dry etching apparatuses; 305 is a cleaning apparatus; 306 and 307 are film deposition apparatuses; 308 is a looped transporter; 309 is an interface; and 310 is a stocking apparatus. Numeral 401 is a lithography apparatus; 402 is an ion implanting apparatus; 403 is a dry etching apparatus; 404 and 405 are film deposition apparatuses; and 406 is an ultra-clean space. Numeral 501 is a lithography apparatus; 502 is a looped transporter; 503a and 503b are linear transporters; 504 and 505 are dry etching apparatuses; 506 and 507 are film deposition apparatuses; 508 is a common exhaust system; 509 is a cleaning and wet etching processing apparatus; 510 is an oxidizing apparatus; 511 and 512 are film deposition apparatuses; 513 is a control system; 514 is an ion implantation apparatus; 517 is an annealing apparatus; 518 is a loading/unloading apparatus; and 519 is a coating apparatus. Numeral 601-1 and 601-2 are inter-apparatus transporters; 602 is a metal film deposition apparatus; 603 is an insulator film deposition apparatus; 604 is a lithography apparatus; 605 is a stocking apparatus; 606 is a metal film dry etching apparatus; 607 is an insulator film dry etching apparatus; and 608 is a loading/unloading apparatus. Numeral 701 and 702 are lithography apparatuses; 703 and 704 are dry etching apparatuses; 705 is a cleaning apparatus; 706 and 707 are film deposition apparatus; 708 is a looped transporter; 709 is an interface; and 710 is a stocking apparatus. Numerals 801a to 801e are processing apparatuses; 802a to 802e are computers; 803a to 803e are computers for managing data bases; 804a to 804e are memories for storing data bases; 805 is a computer for managing a general control data base; 806 is a general managing data base; 808a to 808e are information on result of processing and transporting; 809a to 809e are information on result and scheduling of processing and transporting; 811 and 812 are processing apparatuses; 813 is an inter-apparatus transporter; 814 to 816 are memories; 817 to 826 are semiconductor wafers; and 827 to 836 are data bases. Numerals 901 and 902 are processing apparatuses; 903 is an inter-apparatus transporter; 904 to 906 are memories; 907 to 916 are semiconductor wafers; 917 to 926 are information on result of processing and transporting; 951 and 952 are processing apparatuses for applying two continued processes; 953 to 956 are partial transporting units; 957 to 960 are transporting robots; 961 to 963 are expansible connecting portions; 964 is a laser source; 965 is a laser beam; 966 and 967 are intermediate monitor portions; 968 is final monitoring portion; and 969 and 970 are position adjustment mechanisms.

<Embodiment 1>

This will be described with reference to FIGS. 1 to 12 and Tables 1 and 3. In this embodiment, one layer metal film and a passivation layer are formed on a semiconductor wafer formed with elements and contact-holes.

FIG. 1 is a view showing the embodiment of the inventive system. A metal film deposition apparatus 102, insulator film deposition apparatus 103, lithography apparatus 104, stocking apparatus 105, metal film dry etching apparatus 106, insulator film dry etching apparatus 107, and wafer loading/unloading mechanism 108 are disposed around a looped inter-apparatus single wafer transporter 101. Six pieces of semiconductor wafers # 1 to #6 are continuously processed in the metal film deposition apparatus 102, lithography apparatus 104, metal film dry etching apparatus 106, insulator film deposition apparatus 103, lithography apparatus 104 and insulator film dry etching apparatus 107.

Six pieces of the semiconductor wafers are unloaded to the fabricating system by way of the loading/unloading apparatus 108. First, they are put in a preparing chamber 108-1 of the apparatus 108, and after the atmosphere of the preparing chamber 108-1 is replaced by high purity nitrogen, they are transported to a stocking chamber 108-2 filled with high purity nitrogen by a transporting mechanism provided in the stocking chamber 108-2. The wafers are then unloaded from the stocking chamber 108-2 to the transporter 101 by a transporting mechanism provided in an unloading chamber 108-4 sequentially in the order of the number of the wafers with a time interval of 6 min (which is the specified time interval T in this embodiment) on the basis of a specified starting time. It takes 1 min until the start of the unloading of the wafer #1 after six pieces of the wafers are disposed in the preparing chamber 108-1. The unloading chamber 108-4 is filled with high purity nitrogen. In the transporter 101, the wafers are also transported in a high purity nitrogen atmosphere. The transporter 101 has a mechanism of moving semiconductor wafers along one-direction by a belt, and it takes 4 min for one round. The length of one round is 60 m and the transporting speed is 0.9 km/h. These functions of the transporter 101 can be realized by the conventional transporting technique. A semiconductor wafer can be moved between any two processing apparatuses for 4 min or less by means of this transporter 101. The transporting time of a semiconductor wafer between processing apparatuses, including receiving and unloading times to and from a processing apparatus, is less than the time interval T (6 min).

First, the wafer #1 is transported to the metal film deposition apparatus 102 by the transporter 101. The construction of the metal film deposition apparatus 102 is shown in FIG. 2. The details of the processing and the transporting in the apparatus 102 are shown in FIG. 3. Similarly, the construction and the details of the processing and transporting in the insulator film deposition apparatus 103 are shown in FIGS. 5 and 6; those in lithography apparatus 104 are shown in FIGS. 7 and 8; those in metal film dry etching apparatus 106 are shown in FIGS. 9 and 10; and those in insulator film dry etching apparatus 107 are shown in FIG. 11 and 12.

A transporting mechanism 102-9 of the stocking chamber 102-1 filled with high purity nitrogen receives the wafer #1 from the transporter 101. It is transported to a preparing chamber #1 102-2 filled with nitrogen at the atmospheric pressure by a transporting mechanism 102-10 provided in the preparing chamber #1 102-2, and then the preparing chamber #1 102-2 is evacuated up to 0.06 Pa.

It takes not less than 6 min until the evacuation of the preparing chamber #1 102-2 is completed and the wafer #1 is made possible to be transported to a transporting chamber 102-3, after it is started to be unloaded to the transporter 101 by the transporting mechanisms provided in the unloading chamber 108-4. The processing is started after an elapse of 6 min. The time, at which the wafer #1 is started to be processed in the metal film deposition apparatus 102, is taken as a time To. The wafer #1 waits for a time interval until it is started to be processed after it is made possible be transported to the transporting chamber 102-3.

First, the wafer #1 is transported from the preparing chamber 102-2 to the transporting chamber 102-3 by means of a transporting mechanism 102-11 provided in the transporting chamber 102-3. The pressure in the transporting chamber 102-3 is 6.5.times.10E(-5) Pa. The wafer #1 is then transported to a pre-treatment chamber 102-4 by the transporting mechanism 102-11 and are subjected to the pre-treatment for film deposition. In this embodiment, a natural oxide film or the like on the bottom of a contact-hole of an Si substrate is removed by soft-etching using Ar soft plasma. The pressure is 0.65 Pa and the etching time is 30 sec. After evacuation of the pre-treatment chamber 102-4, the wafer #1 is transported to a sputtering chamber #1 102-5 by way of the transporting chamber 102-3 by a transporting mechanism 102-11 provided in the transporting chamber 102-3. In the sputtering chamber #1 102-5, the wafer #1 is formed with a barrier film, which is TiN in this embodiment, to a thickness of 150 nm by a reactive sputter using a discharge gas of Ar and N.sub.2. In the film formation, the pressure is 0.5 Pa, and the processing time is 1 min. The wafer # 1 is then transported to a sputtering chamber #2 102-6 by way of the transporting chamber 102-3 by the transporting mechanism 102-11. In the sputtering chamber #2 102-6, an Al-1%Si-0.5%Cu alloy film is deposited. The thickness of the Al alloy film is 700 nm, the pressure for the film deposition is 0.5 Pa, and the processing time is 1 min. After that, the wafer #1 is transported to a preparing chamber #2 102-7 with a pressure of 0.06 Pa by way of the transporting chamber 102-3 by the transporting mechanism 102-11. After the pressure of the preparing chamber #2 102-7 is returned to the atmospheric pressure using nitrogen, the wafer #1 is transported to an unloading chamber 102-8 filled with high purity nitrogen by a transporting mechanism 102-12 provided in the preparing chamber #2 102-7. It takes not less than 6 min, that is, 5.7 min until the wafer #1 is transported to the unloading chamber 102-8 and is made possible to be transported to the transporter 101 by a transporting mechanism 102-13 provided in the unloading chamber 102-8, after it is started to be transported to the transporting chamber 102-3 from the preparing chamber #1 102-2. The wafer #1 is started to be transported to the next processing apparatus after an elapse of 6 min. The wafer #1 waits for a time interval until it is started to be transported after it is made possible to be unloaded to the transporter 101.

The time, at which the wafer #1 is started to be processed in the metal film deposition apparatus 102, is taken as the time To. FIG. 4 is a view for explaining the details of the processing and transporting applied to the wafers #1 and #2 for a time period of 2T (=12) min after the time To. The processing time of the wafer #1 in the metal film deposition apparatus 102 is the time from To to (To+T), that is, the time T (=6) min. The transporting time of the wafer #1 from the metal film deposition apparatus 102 to the lithography apparatus 104 is the time from (To+T) to (To+2T), that is, the time T min. This transporting will be described. First, at the time (To+T), the wafer #1 is started to be unloaded to the transporter 101 by means of a transporting mechanism 102-13 (FIG. 2) provided in the unloading chamber 102-8, and it is transported to the subsequent lithography apparatus 104 by the transporter 101. It is transported from the transporter 101 to a stocking chamber 104-1 by means of a transporting mechanism 104-7 provided in the stocking chamber 104-1 (FIG. 7). The wafer #1 waits for a time interval until the time (To+2T) after the wafer #1 is transported to the stocking chamber 104-1 and it is made possible to be transported to a coating chamber 104-2 of the lithography apparatus 104 by means of a transporting mechanism 104-8.

FIG. 4 also shows the details of the processing and transporting applied to the wafer #2 for a time interval from the time To to (To+2T). The wafer #2 is loaded to the system by means of the loading/unloading apparatus 108 while being delayed by T min, and which is subjected to the same processing and transporting operations as those for the wafer #1. It takes a time interval T min, from the time To to (To+T), to transport the wafer #2 from the loading/unloading apparatus 108 to the metal film deposition apparatus 102. It takes a time interval T min, from the time (To+T) to (To+2T), to process the wafer #2 in the metal film deposition apparatus 102.

Next, the processing for the wafer #1 in the lithography apparatus 104 will be fully described with reference to FIGS. 7 and 8. First, the wafer #1 is transported from a stocking chamber 104-1 to a coating chamber 104-2 by means of a transporting mechanism 104-8, and which is coated with a resist by a roller type resist coater. It takes 40 sec to coat the wafer #1 with the resist to a thickness of 1.2 .mu.m. The transporting mechanism 104-8 and the like are all contained in a housing (not shown) filled with nitrogen, so that the wafer is not exposed to the atmospheric air in the processing apparatus 104. The wafer #1 is then transported to a baking chamber 104-3 by means of a transporting mechanism 104-9, and is subjected to heat treatment (120.degree. C..times.40 sec) to harden the resist. It is transported from the baking chamber 104-3 to an exposing chamber 104-4 by means of a transporting mechanism 104-10, to be subjected to exposure using the infrared ray of mercury as a light source. The function of the exposing chamber 104-4 is the same as that of the usual stepper. The exposure for the wafer #1 takes 2 min. The wafer #1 is then moved to a developing chamber 104-5 by means of a transporting mechanism 104-11, and is subjected to developing by exposing the surface to a developing agent. The developing for the wafer #1 takes 80 sec. It is then transported to a dry chamber (serving as an unloading chamber) 104-6 by means of a transporting mechanism 104-12. It takes 5.3 min, which is less than the time T (6 min) of the inventive system, until the wafer #1 is made possible to be transported by a transporting mechanism 104-13 provided in the dry chamber 104-6, after it is started to be moved from the stocking chamber 104-1 to the coating chamber 104-2. The wafer #1 waits until an elapse of 6 min, that is, it is transported after an elapse of 6 min.

The wafer #1 is unloaded to the transporter 101, and is transported to the metal film dry etching apparatus 106. It is moved to a stocking chamber 106-1 filled with nitrogen by means of a transporting mechanism 106-9 provided in the stocking chamber 106-1 (FIG. 9), and is further transported to a preparing chamber #1 106-2 by means of a transporting mechanism 106-10. It takes a time less than 6 min (T of the system) until the preparing chamber #1 106-2 is evacuated up to 0.65 Pa and the wafer #1 is made possible to be moved to a transporting chamber 106-3, after it is started to be transported. The wafer #1 waits until an elapse of 6 min, that is, it is started to be processed after an elapse of 6 min.

The processing for the wafer #1 in the metal film dry etching chamber 106 will be described with reference to FIGS. 9 and 10. The wafer #1 in the preparing chamber #1 106-2 is transported to the transporting chamber 106-3 by means of a transporting mechanism 106-11 provided in the transporting chamber 106-3, and which is further transported to an etching chamber 106-4. The pressure of the transporting chamber 106-3 is 0.01 Pa. In an etching chamber 106-4, a multi-layer film of an Al alloy film/TiN film is etched. It takes 40 sec to etch the multi-layer film using a mixed gas of chlorine and BCl.sub.3. The pressure upon etching is 0.4 Pa. The etching chamber 106-4 is evacuated to 0.015 Pa, and the wafer #1 is transported to an anticorrosive treatment chamber 106-5 through the transporting chamber 106-3 by means of a transporting mechanism 106-11, to be subjected to anticorrosive treatment by CHF.sub.3 for the Al alloy film. The pressure upon the anticorrosive treatment is 0.6 Pa, and the treatment takes 30 sec. The wafer #1 is then transported from the anti-corrosive treatment chamber 106-5 to an ashing chamber 106-6 through the transporting chamber 106-3 by means of the transporting mechanism 106-11. The resist is removed by ashing using oxygen plasma in the ashing chamber 106-6. The pressure upon the ashing is 50 Pa, and the ashing takes 30 sec. The wafer #1 is then transported to a preparing chamber #2 106-7 through the transporting chamber 106-3 by means of the transporting mechanism 106-11. The preparing chamber #2 106-7, after receiving the wafer #1, is filled with high purity nitrogen at the atmospheric pressure. After that, the wafer #1 is transported to an unloading chamber 106-8 filled with high purity nitrogen by means of a transporting mechanism 106-12, and waits for transporting. It takes 5 min until the wafer #1 is made possible to be transported after it is started to be processed. The wafer #1 waits for 1 min.

The wafer #1 is unloaded onto transported 101 by a transporting mechanism 106-13 and moved from the metal film dry etching apparatus 106 to the insulator film deposition apparatus 103.

The processing for the wafer #1 in the insulator film deposition apparatus 103 will be described with reference to FIGS. 5 and 6. The wafer #1 is placed in a film deposition chamber #1 103-4 of the insulator film deposition chamber 103 by transporting mechanism 103-8, and an SiO.sub.2 film is deposited by plasma chemical vapor deposition (CVD) using TEOS (Tetra Ethyl Ortho Silicate) and oxygen as a source gas. The SiO.sub.2 film thus deposited is used as an interlayer insulator film for metallization. In a film deposition chamber #2 103-5, an Si.sub.3 N.sub.4 film is deposited by plasma CVD using SiH.sub.4 and NH.sub.3 as a source gas. The Si.sub.3 N.sub.4 film thus deposited is used as the uppermost passivation layer of the wafer. Now, the nitride film is formed on the wafer #1. In this insulator film deposition apparatus 103, only the film deposition is performed, and this processing does not take a lot of time so much; accordingly, the wafer #1 waits for processing in the stocking chamber 103-1, and is started to be processed.

First, the wafer #1 is moved from the stocking chamber 103-1 to a preparing chamber #1 103-2 by means of a transporting mechanism 103-9, thus starting the processing. It is transported from the preparing chamber #1 103-2 to a transporting chamber 103-3 by means of a transporting mechanism 103-10, and is further transported to a film deposition apparatus #2 103-5. In this chamber #2 103-5, an Si.sub.3 N.sub.4 film is deposited on the wafer #1 to a thickness of 0.5 .mu.m by the above-described plasma CVD. The pressure is 50 Pa, and the film deposition takes 1 min. The wafer #1 is then transported to a preparing chamber #2 103-6 through the transporting chamber 103-3 by means of a transporting mechanism 103-10. The preparing chamber #2 103-6 is filled with nitrogen at the atmospheric pressure, and then the wafer #1 is transported to an unloading chamber 103-7 filled with nitrogen by means of a transporting mechanism 103-11, and it waits for unloading to the transporter 101 (FIG. 1) by a transporting mechanism 103-12. It takes 4 min until the wafer #1 is made possible to be unloaded after it is started to be processed. Accordingly, the wafers #1 waits for 2 min. After the wafer #1 is moved from the film deposition chamber #2 103-5 to the transporting chamber 103-3, the film deposition chamber #2 103-5 is cleaned by NF3 plasma, and is prepared for the next semiconductor wafer.

The wafer #1 is transported from the insu