Integrated circuit processing system

5044871
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Inventors

Davis, Cecil J.
Matthews, Robert
Bowling, Robert A.

Application #

143918

Filed

Jan-13-1988

Published

Sep-3-1991

Current US Class

118/500
118/719
414/217
414/331.02
414/416.03
414/805
414/939
414/940

International Classes

B65G 049/05

Field of Search

414/744.2 414/217 414/416 414/609 414/610 414/403 414/404 414/220 414/225 414/222 414/786 414/282 414/728 414/331 118/728 118/729 118/733 118/50 118/50.1 118/500 118/719

Assignee

Texas Instruments Incorporated (Dallas, TX)

Examiners

Werner; Frank E.

Attorney, Agent or Firm

Barndt; B. Peter, Comfort; James T., Sharp; Melvin

US Patent References

4178113   Buffer storage app...
4532970   Particle-free docka...
4544317   Vacuum-to-vacuum...
4546897   Inert atmosphere tr...
4579080   Induction heated re...
4584045   Apparatus for conv...
4592308   Solderless MBE syst...
4636128   Semiconductor slic...
4664578   Semiconductor sub...
4674939   Sealed standard int...
4824309   Vacuum processin...

Referenced by:

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Citation

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Abstract
A vacuum-tight wafer carrier, and a load lock suitable for use with this wafer carrier. The wafers are supported at each side by a slightly sloping shelf, so that minimal contact (line contact) is made between the wafer surface and the surface of the shelf. This reduces generation of particulates by abrasion of the surface of the wafer. The carrier also contains elastic elements to restrain the wafers from rattling around, which further reduces the internal generation of particulates. When the wafer carrier is placed into the load lock, its body is lowered from beneath its cover through an aperture into a lower chamber, where wafers are loaded and unloaded under vacuum; the carrier cover remains covering the aperture into the lower chamber, so that the wafers never see any surface which is directly exposed to atmosphere. A wafer transport arm mechanism permits interchange of wafers among one or more processing stations and one or more load locks of this type.
 
Claims
What is claimed is:

1. A method for fabricating integrated circuits, comprising the steps of:

providing a plurality of wafers in a vacuum sealable wafer carrier, said wafer carrier comprising a bell jar shape cover which is vacuum sealable to a body thereof, said bell jar shape cover being removable from said body in a direction which is substantially normal to the plane of wafers supported in said body;

placing said wafer carrier into a vacuum sealable load lock upper chamber having a partial floor with an aperture therein and a stage positioned below said aperture in close proximity to said floor;

pumping down said load lock upper chamber to a pressure less than 10 to the -4 Torr;



Description
BACKGROUND AND SUMMARY OF THE INVENTION

The present invention relates to apparatus for manufacturing of integrated circuits.

One of the basic problems in integrated circuit manufacturing is particulates. This problem is becoming more and more difficult, because of two trends in integrated circuit processing: First, as device dimensions become smaller and smaller, it is necessary to avoid the presence of smaller and smaller particles. This makes the job of making sure that a clean room is really clean increasingly difficult. For example, a clean room which is of class 1 (has one particle per cubic foot) for particles of one micron and larger may well be class 1000 or worse if particle sizes down to 100 angstroms are counted.

Second, there is increased desire to use large size integrated circuit patterns: for example, integrated circuit sizes larger than 50,000 square mils are much more commonly used now than they were five years ago.

Thus, particulates are not only an extremely important source of loss in integrated circuit manufacturing, but their importance will increase very rapidly in the coming years. Thus, it is an object of the present invention to provide generally applicable methods for fabricating integrated circuits which reduce the sensitivity of the process to particulate contamination.