Processing apparatus

4836905
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Inventors

Davis, Cecil J.
Abernathy, Joseph V.
Matthews, Robert T.
Hildenbrand, Randall C.
Simpson, Bruce
Bohlman, James G.
Loewenstein, Lee M.
Jones, John I.

Application #

075018

Filed

Jul-16-1987

Published

Jun-6-1989

Current US Class

118/719
156/345.51
204/192.12
204/298.25
414/936
414/937

International Classes

C23C 013/34

Field of Search

156/345 156/643 204/298 204/192.1 204/192.12 414/217 414/219 414/222 414/223 414/226 118/719 118/729

Assignee

Texas Instruments Incorporated (Dallas, TX)

Examiners

Nguyen; Nam X.

Attorney, Agent or Firm

Rogers; Joseph E., Comfort; James T., Sharp; Melvin

US Patent References

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4340462   Adjustable electrod...
4405435   Apparatus for perfo...
4431473   RIE Apparatus utili...
4473455   Wafer holding app...
4584045   Apparatus for conv...
4595484   Reactive ion etchin...
4670126   Sputter module for...

Referenced by:

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Cite This Patent

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Abstract
A processing apparatus and method which permits sputter deposition and which is compatible with a vacuum processing system wherein the wafers are largely transferred and processed in the face down position. This includes an additional wafer movement, wherein, after a wafer has been emplaced face down, in a position where it can be clamped against the susceptor, the susceptor is rotated from its approximately horizontal position up to a more nearly vertical position. While the wafer is in the more nearly vertical position, sputter deposition may be performed. In situ or remote plasma capability is usefully provided in the bottom part of the chamber, so that a dry deglaze or cleanup step can be performed while the wafer is in its substantially horizontal position, followed by a sputter deposition after the wafer has been moved to its more nearly vertical position.
 
Claims
What is claimed is:

1. An apparatus for processing of wafers, comprising:

(a) a vacuum processing chamber having a top processing chamber having means for performing a first processing step and an upper processing space having means for performing a second processing step within said vacuum processing chamber;

(b) a wafer support within said vacuum processing chamber, said wafer support being capable of supporting a wafer in a substantially face down position with substantially no damage to structures on the face of said wafer in the top processing chamber while a first processing step is being performed; and

(c) said wafer support being movable to rotate said wafer from said substantially face down position in said top process chamber into a more nearly vertical position in said upper processing space where a second processing step can be performed.



Description
BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will be described with reference to the accompanying drawings, wherein:

FIG. 1 shows a sample embodiment of a load lock which is compatible with vacuum processing and transport of semiconductor integrated circuit wafers.

FIG. 2 shows a graph of the time required to fall through air at various pressures for particulates of various sizes.

FIG. 3 shows a sample wafer transfer structure, in a process station, wherein the wafer is placed onto three pins by the transfer arm 28 reaching through the inter-chamber transfer port 30 from the adjacent vacuum load lock chamber 12.

FIG. 4 shows a closer view of a sample embodiment of a multi-wafer vacuum wafer carrier 10, docked onto the position registration platform 18 inside a load lock like that of FIG. 1.

FIGS. 5A and 5B show a plan view of a sample process stations including process modules and wafer transfer stages, and a load locks.

FIG. 6 shows a configuration for a process module, which can be used as one of the process modules inside the process station shown in FIGS. 5A and 5B.