Dry etching method

6576152
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Inventors

Matsutani, Tetsuya

Application #

899548

Filed

Jul-6-2001

Published

Jun-10-2003

Current US Class

216/11
216/58
216/63
216/67
216/68
216/72
216/74
216/75
216/79
438/706
438/707
438/710
438/719
438/720
438/733
438/735
438/737
438/738
438/742

International Classes

C23F 007/00

Field of Search

216/11 216/58 216/63 216/67 216/68 216/72-74 216/75 216/79 438/706 438/707 438/710 438/719 438/720 438/733 438/735 438/737 438/738 438/742

Assignee

Matsushita Electric Industrial Co., Ltd. (JP)

Examiners

Gulakowski; Randy

Attorney, Agent or Firm

Parkhurst & Wendel, L.L.P.

US Patent References

4377734   Method for forming...
4836886   Binary chlorofluoro...
4836887   Chlorofluorocarbon...
5108542   Selective etching m...
5112435   Materials and meth...
5147500   Dry etching method
5164331   Method of forming...
5212147   Method of forming...
5609775   Dry etch process for...
5767021   Dry etching method...
5846886   Metal film etching...
5856239   Tungsten silicide/ t...
5866483   Method for anisotro...
5975685   Ink jet recording he...
6136211   Self-cleaning etch...
6258637   Method for thin fil...
6277733   Oxygen-free, dry pl...
6413874   Method and appar...
6432832   Method of improvin...
 

Referenced by:

View Backward References

Other References

S. Arai et al., "Intensity Distribution of Plasma Emission in Low Temperature Etching," 1989 Autumn JSAP Annual Meeting, No. 2, p 464. K. Tsujimoto, et al., "Low Temperature etching (XI)-W Etching," 1989 Autumn JSAP Annual Meeting, No. 2, p 464. K. Iizuka, et al., "Effect of Water Temperature on Wsix/poly Si RIE," 1989 Autumn JSAP Annual Meeting, No. 2, p 464. Y. Kato, et al. "Low-Temperature RIE of CVD-W/TiN/Ti," 1991 Spring JSAP Annual Meeting, No. 2, p 503. S. Iida, et al., "Low-Temperature Etching of CVD-W," 1992 Autumn JSAP Annual Meeting, No. 2, p 465. H. Hayashi, et al., "High Temperature W Etching By Using Cl.sub.2 or Hbr," 1992 Autumn JSAP Annual Meeting, No. 2, p 465. H. Kawakami, et al., "High Temperature Etching of Tungsten Poly-metal Gate," 1998 Autumn JSAP Annual Meeting, No. 2, p 640.

Citation

Cite This Patent

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Abstract
In a dry etching method for etching a structure obtained by successively depositing, on a substrate, a gate insulating film, a silicon base film, a tungsten film or an alloy film containing tungsten, the dry etching includes a first process of dry-etching the tungsten film or the alloy film including tungsten, and a second process of dry-etching the silicon base film, and the first process employs, as an etching gas, a gas mixture obtained by mixing O.sub.2 gas into a gas including at least C and F, with the flow ratio of the O.sub.2 gas being 10.about.50% by volume percentages. This dry etching method realizes highly-precise dry etching by which a vertical configuration of the poly-metal structure is obtained, and the selection ratio of W with respect to poly-Si can be controlled and, moreover, penetration through the underlying gate oxide film is prevented.
 
Claims
What is claimed is:

1. A dry etching method for etching a poly-metal electrode gate structure obtained by successively depositing, on a substrate, a gate insulating film, a film that consists of silicon, and a tungsten film, wherein:

said dry etching includes a first process of dry-etching the tungsten film until the surface of the film that consists of silicon is oxidized, and a second process of dry-etching the silicon base film, wherein

said first process employs, as an etching gas, a gas mixture obtained by mixing O.sub.2 gas into a gas including at least CF.sub.4, with the flow ratio of the O.sub.2 gas being 10 to 50% by volume percentages and said second process employs, as an etching gas, a gas mixture in which no fluorinated hydrocarbon is used.



Description
FIELD OF THE INVENTION

The present invention relates to a dry etching method and, more particularly, to improved anisotropic dry etching on a lamination of a silicon base film, a tungsten film, and a tungsten alloy film, which dry etching is adopted mainly in a process of manufacturing a high-performance semiconductor device having a gate width narrower than 0.18 .mu.m rules.

BACKGROUND OF THE INVENTION

In recent years, semiconductor devices have remarkably grown in performance, and further speedup and reduction in power consumption have been demanded.

For example, in a fine semiconductor device having a gate width narrower than 0.18 .mu.m rules, for further improvement in performance of transistors, there has been promoted a transition from a conventional N.sup.+ single gate structure to a dual gate structure in which a P.sup.+ electrode is used for a P channel transistor while an N.sup.+ electrode is used for an N channel transistor. On the other hand, for further speedup and reduction in power consumption, reduction in resistance of gate electrodes has been demanded.
 
  A multi-stage cooler is formed from monolithically integrated thermionic and thermoelectric coolers, wherein the thermionic and thermoelectric coolers...  The present invention provides a dry chemical-mechanical polishing method to perform etching in efficient manner. The dry chemical-mechanical polishing...