Wafer support system

A wafer support system comprising a segmented susceptor having top and bottom sections and gas flow passages therethrough. A plurality of spacers projecting from a recess formed in the top section of the susceptor support a wafer in spaced relationship with respect to the recess. A sweep gas is introduced to the bottom section of the segmented susceptor and travels through the gas flow passages to exit in at least one circular array of outlets in the recess and underneath the spaced wafer. The sweep gas travels radially outward between the susceptor and wafer to prevent back-side contamination of the wafer. The gas is delivered through a hollow drive shaft and into a multi-armed susceptor support underneath the susceptor. The support arms conduct the sweep gas from the drive shaft to the gas passages in the segmented susceptor. The gas passages are arranged to heat the sweep gas prior to delivery underneath the wafer. Short purge channels may be provided to deliver some of the sweep gas to regions surrounding the spacers to cause a continuous flow of protective purge gas around the spacers. A common bottom section may cooperate with a plurality of different top sections to form segmented susceptors suitable for supporting various sized wafers.

 

What is claimed:

1. An apparatus for processing a semiconductor wafer, comprising:

a processing chamber;

a generally horizontal, rotatably mounted susceptor positioned in the chamber;

one or more spacers to support a wafer spaced above the susceptor;

a ring surrounding said susceptor and having a horizontal cross-section having a generally rectangular exterior;

heat sources to heat the susceptor and the ring; and

a process gas injector for flowing gas across the upper surface of the heated wafer and the ring to be uniformly deposited on the wafer;

said susceptor including passages for introducing sweep gas between the susceptor and the wafer to provide backside protection to the wafer.

2. The apparatus of claim 1, wherein said heat sources include a heat bank spaced above the wafer and configured to define a generally rectangular heat pattern aligned with said ring.

3. The apparatus of claim 2, wherein said heat sources include a heat bank spaced below the susceptor and configured to define a generally rectangular heat pattern aligned with said ring.

4. The apparatus of claim 1, wherein said chamber in the area of the susceptor and the ring has a generally rectangular cross section generally perpendicular to the gas flow.

5. The apparatus of claim 1, including a plurality of spacers, the spacers each comprising a flat upper surface.

6. The apparatus of claim 5, wherein the flat upper surface has a diameter between about 0.025 inch and 0.045 inch.

7. The apparatus of claim 5, further comprising a rounded edge surrounding the flat upper surface.

8. An apparatus for processing a semiconductor wafer comprising:

a chamber;

a susceptor in said chamber;

a process gas inlet to said chamber to flow processing gas into the chamber and across an upper surface of the susceptor;

a plurality of spacers protruding above an upper surface of a recess formed in said susceptor and supporting a wafer with a gap between the wafer and the susceptor, said susceptor being located so that said process gas flows across the upper surface of said wafer, said spacers each comprising a flat upper surface surrounded by a rounded edge;

said susceptor upper surface having one or more sweep gas outlets; and

one or more gas channels in said susceptor for flowing sweep gas through said outlet and into the gap beneath the wafer to prevent process gas from flowing into said gap.

9. The apparatus of claim 8, wherein said susceptor is formed of two sections that fit together to form said channels.

10.The apparatus of claim 8, including a susceptor support having arms, at least one of said arms including a passage for conducting gas to the channels in said susceptor.

11. The apparatus of claim 8, including apertures in said susceptor for receiving and retaining said spacers, said apertures being sized slightly larger than said spacers to provide some clearance therebetween, wherein some of said channels lead to said apertures to allow gas flow around said spacers into the gap beneath the wafer.

12. The apparatus of claim 8, wherein the flat upper surfaces each have a diameter between about 0.025 inch and 0.045 inch.

13. An apparatus for processing a semiconductor wafer at an elevated temperature comprising:

a substantially disc-shaped susceptor having one or more gas channels formed therein with one or more gas inlets to said channels, said inlets open to a lower surface of said susceptor, and one or more gas outlets open to an upper surface of said susceptor; and

a support for said susceptor including a plurality of support arms having upper ends to engage the lower surface of said susceptor to support the susceptor, one or more of said arms being tubular so that gas may be conducted through said tubular arms into said inlets.

14. The apparatus of claim 13, wherein the upper ends of said support arms drivingly engage the lower surface of the susceptor so that rotation of the said arms rotates said susceptor.

15. The apparatus of claim 13, wherein said susceptor is formed of two mating sections, with said channels being formed in the surface of one of said sections, facing the other of said sections, said channels being open to the other of said sections so that said other section forms a wall of said channels.

16. The apparatus of claim 15 wherein said gas inlets are located spaced outwardly from the center of the susceptor, and said gas outlets are located spaced radially outwardly from the center of the susceptor and radially inward from said gas inlets, and wherein said channels extend nonlinearly between said inlets and said outlets.

17. The apparatus of claim 16, wherein said channels extend outwardly from said inlets, continue circumferentially adjacent the periphery of the susceptor lower section and finally are directed radially inwardly to said gas outlets.

18. The apparatus of claim 15, wherein said mating sections comprise a substantially disc shaped lower section and a substantially disc shaped upper section having a lower surface in engagement with an upper surface of said lower section, said apparatus including one or more spacers extending upwardly from the upper surface of said susceptor to support a wafer slightly spaced from the susceptor to permit gas from said outlets to flow beneath the wafer.

19. The apparatus of claim 18, comprising apertures in said upper section for receiving and retaining said spacers, said apertures being sized slightly larger than said spacers to provide some clearance therebetween, wherein some of said channels are formed in the lower surface of said upper section and lead to said apertures to allow gas flow around said spacers, and wherein some of said channels are formed by grooves in the upper surface of said lower section with said grooves being closed by the lower surface of said upper section, the grooves leading to said outlets.

20. The apparatus of claim 18, wherein said susceptor upper surface has a shallow recess with a depth greater than the height of said spacers so that the wafer to be positioned thereon fits within said upper recess and does not project substantially above a top surface of said susceptor.

21. The apparatus of claim 18, wherein said one or more spacers comprises a plurality of pins having flat upper surfaces each with a width between about 0.025 inch and 0.045 inch.

22. The apparatus of claim 13, including a plurality of spacers extending upwardly from the upper surface of said susceptor to support a wafer spaced from the susceptor to permit gas from said outlets to flow beneath the wafer.

23. The apparatus of claim 22, including apertures in said susceptor for receiving and retaining said spacers, said apertures being sized slightly larger than said spacers to provide some clearance therebetween, and wherein some of said channels are in communication with said apertures to allow gas flow around said spacers.

24. An apparatus for chemical vapor deposition a semiconductor wafer comprising:

a deposition chamber having a process gas inlet for injecting process gases into the chamber;

a single susceptor in the chamber for supporting a semiconductor wafer; and

a support for said susceptor including a plurality of support arms, one or more of said arms being tubular and in registry with inlets in the susceptor so that gas may be conducted through said tubular arms into said inlets.

25. The apparatus of claim 24, including a tubular shaft supporting said arms and in communication with the support arms so that gas may be conducted upwardly through the shaft and through the support arms.

26. A combination for supporting different sized wafers in a semiconductor processing environment, comprising:

a first substantially disk-shaped upper susceptor section having a lower surface and a shallow wafer recess in an upper surface sized to concentrically receive a first wafer to be processed, said first upper susceptor section having a plurality of spacers in said wafer recess; and

a second disk-shaped upper susceptor section having a lower surface and a shallow wafer recess in an upper surface sized to receive a wafer to be processed, having a different diameter from said first wafer, said second upper susceptor section having a plurality of spacers in said wafer recess, and wherein the lower surfaces of said first and second upper sections are identical, at least one of said spacers in said first and second upper susceptor sections having a flat upper surface surrounded by a rounded edge.

27. A susceptor for supporting a wafer in a semiconductor processing environment, comprising:

a substantially disk-shaped upper section having a shallow wafer recess in a top surface with a diameter depending on the size of a wafer selected to be processed, and a recess in a bottom surface for mating with a lower section; and

one or more wafer spacers in said upper section recess protruding above the upper surface of said recess for supporting a wafer, at least one of said spacers comprising a flat upper surface surrounded by a rounded edge.

28. A pin configured for supporting a semiconductor wafer spaced over a wafer support structure, the pin comprising a flat upper surface having a width between about 0.025 inch and 0.045 inch and a rounded edge surrounding said flat upper surface.

29. The pin of claim 28, defining a height between the support structure and the flat upper surface of between about 0.010 inch and 0.200 inch.

30. The pin of claim 29, defining a height between the support structure and the flat upper surface of between about 0.060 inch and 0.090 inch.

31. The pin of claim 28, formed of a material selected from the group consisting of quartz, silicon carbide, silicon nitride, boron carbide, boron nitride, aluminum nitride, and zirconium carbide.

32. The pin of claim 31, coated with a material selected from the group consisting of Si, Si.sub.3 N.sub.4, SiO.sub.2 or SiC.

33. The pin of claim 28, wherein the flat upper surface is polished.

FIELD OF THE INVENTION

The present invention relates to supports for wafers in semiconductor processing chambers and, more particularly, to a system for supporting a wafer above a susceptor within a chemical vapor deposition chamber.

BACKGROUND OF THE INVENTION

High-temperature ovens, or reactors, are used to process semiconductor wafers from which integrated circuits are made for the electronics industry. A circular wafer or substrate, typically made of silicon, is placed on a wafer support called a susceptor. Both the wafer and susceptor are enclosed in a quartz chamber and heated to high temperatures, such as 600.degree. C. (1112.degree. F.) or higher, frequently by a plurality of radiant lamps placed around the quartz chamber. A reactant gas is passed over the heated wafer, causing the chemical vapor deposition (CVD) of a thin layer of the reactant material on the wafer. Through subsequent processes in other equipment, these layers are made into integrated circuits, with a single layer producing from tens to thousands of integrated circuits, depending on the size of the wafer and the complexity of the circuits.

If the deposited layer has the same crystallographic structure as the underlying silicon wafer, it is called an epitaxial layer. This is also sometimes called a monocrystalline layer because it has only one crystal structure.

Various CVD process parameters must be carefully controlled to ensure the high quality of the resulting semiconductor. One such critical parameter is the temperature of the wafer during the processing. The deposition gas reacts at particular temperatures and deposits on the wafer. If the temperature varies greatly across the surface of the wafer, uneven deposition of the reactant gas occurs.

In certain batch processors (i.e., CVD reactors which process more than one wafer at a time) wafers are placed on a relatively large-mass susceptor made of graphite or other beat-absorbing material to help the temperature of the wafers remain uniform. In this context, a "large-mass" susceptor is one which has a large thermal mass relative to the wafer. Mass is equal to the density times volume. The thermal mass is equal to mass times specific heat capacitance.

One example of a large-mass susceptor is shown in U.S. Pat. No. 4,496,609 issued to McNeilly, which discloses a CVD process wherein the wafers are placed directly on a relatively large-mass, slab-like susceptor and maintained in intimate contact to permit a transfer of heat therebetween. The graphite susceptor supposedly acts as a thermal "flywheel" which transfers heat to the wafer to maintain its temperature uniform and relatively constant. The goal is to reduce transient temperature variations around the wafer that would occur without the "flywheel" effect of the susceptor.

In recent years, single-wafer processing of larger diameter wafers has grown for a variety of reasons including its greater precision as opposed to processing batches of wafers at the same time. Although single-wafer processing by itself provides advantages over batch processing, control of process parameters and throughput remains critical. In systems in which the wafer is supported in intimate contact with a large-mass, slab-like susceptor, the necessity of maintaining uniform susceptor temperature during heat-up and cool-down cycles limited the rate at which the temperature could be changed. For example, in order to maintain temperature uniformity across the susceptor, the power input to the edges of the susceptor had to be significantly greater than the power input to the center due to the edge effects.

Another significant problem faced when attempting to obtain high-quality CVD films is particulate contamination. One troublesome source of particulates in the CVD of metals and other conductors is the film that forms on the back side of the wafer under certain conditions. For example, if the wafer back side is unprotected or inadequately protected during deposition, a partial coating of the CVD material forms thereon. This partial coating tends to peel and flake easily for some types of materials, introducing particulates into the chamber during deposition and subsequent handling steps. One example of protecting the back side of a wafer during processing is given in U.S. Pat. No. 5,238,499 to van de Ven, et al. In this patent an inert gas is introduced through a circular groove in the peripheral region of a support platen. In U.S. Pat. No. 5,356,476 to Foster, et al., a semiconductor wafer processing apparatus is shown, including a plurality of ducts for introducing helium or hydrogen around the perimeter of a wafer to prevent flow of reactant gases downwardly into a gap between the perimeter of the wafer and a wafer support lip. The aforementioned devices, however, share the feature of rather large wafer support platens, characterized by the aforementioned detrimental high thermal mass.

Presently, there is a need for an improved wafer support system while ensuring temperature uniformity across the wafer surface.

SUMMARY OF THE INVENTION

The present invention embodies a susceptor which supports a wafer spaced therefrom and effectively decouples conductive beat transfer between the two elements. The wafer is supported on one or more spacers in a recess preferably in an upper surface of the susceptor, the top plane of the wafers preferably being approximately level with an outer ledge of the susceptor. In one arrangement, spacer pins are utilized, and in another a single spacer ring is used. The susceptor preferably includes a plurality of interior passages opening into the recess at a plurality of small sweep gas holes. A sweep gas flows through the susceptor and out the holes and protects the back side of the wafer from deposition gas and particulate contamination. The sweep gas is heated as it flows through the susceptor so as not to cause localized cooling of the wafer and possible areas of slip.

In one embodiment, the susceptor is formed by top and bottom mating sections and the internal passages are formed by grooves in one of the juxtaposed surfaces of the two sections. Desirably, a multi-armed member supports and rotates the susceptor, the member preferably being substantially transparent to radiant energy. The arms of the support member are preferably hollow and deliver sweep gas to the lower surface of the susceptor at apertures in communication with the internal passages. Some of the sweep gas may be diverted to exit the susceptor proximate the spacer pins to provide sweep gas protection therearound at all times.

In another aspect of the invention the spacer ring mentioned is located to be positioned beneath the periphery of the wafer and serves to reduce the size of the sweep gas outlet from beneath the wafer and to block deposition gas from flowing to the wafer backside. The ring is configured to support the wafer in one arrangement. Preferably, the ring and the susceptor are configured to form sweep gas outlet passages. As another embodiment, the ring is spaced slightly from the wafer to provide a thin annular outlet for the sweep gas, and the wafer is supported by pins.

In one aspect, the invention provides a susceptor to be positioned in a high temperature processing chamber for supporting a wafer to be processed. The susceptor includes a thin, substantially disc shaped lower section and a thin, substantially disc shaped upper section having a lower surface in engagement with an upper surface of said lower section. One of the sections has an outer diameter larger than that of the other section, the larger section having a recess in which the other section is positioned. One or more gas channels are defined by the engaging surfaces of the sections. The susceptor includes one or more gas inlets in the lower section opening to its lower surface and the channels. One or more gas outlets in the upper section open to the upper surface of the upper section in an area beneath that in which a wafer to be processed is to be positioned. The mating recess is preferably formed in a lower surface of the upper section. In one form, the channels are formed by grooves in the upper surface of the lower section with the grooves being closed by the lower surface of the upper section. There are preferably three of the inlets each opening to the channels, the channels being interconnected to allow gas flow throughout.

In accordance with another aspect, the invention provides an apparatus for chemical vapor deposition on a semiconductor wafer comprising a deposition chamber having a process gas inlet for injecting process gases into the chamber. A single susceptor is provided in the chamber. A support for the susceptor includes a central shaft positioned below the susceptor axis and a plurality of support arms extending radially and upwardly from the shaft with the arms having upper ends adapted to engage the lower surface and support the susceptor. One or more of the arms are tubular and in registry with inlets in the susceptor so that gas may be conducted through the tubular arms into the inlets.

The present invention also provides a method of supporting a semiconductor wafer in a processing chamber and conducting gas flow beneath the wafer. The method comprises the steps of positioning the wafer on a plurality of spacers protruding upwardly from an upper surface of the susceptor to support the wafer and form a gap between the wafer and the upper surface of the susceptor. The susceptor is supported on a plurality of arms having upper ends engaging a lower surface of the susceptor. Gas flows through one or more of the arms into passages in the susceptor which open to the gap. The gas is allowed to flow outwardly beyond the periphery of the wafer. Desirably, the spacers are positioned in apertures in the susceptor, and some of the gas flows from the arms through the susceptor passages and into the gap via the apertures surrounding the spacers.

In another aspect of the invention, an apparatus for supporting wafers in a semiconductor processing environment includes a lower section and a plurality of disk-shaped upper sections each adapted to register concentrically with the lower section. The upper sections each have a shallow wafer recess sized differently than the other upper sections to enable selection of the upper section depending on the size of wafer to be processed. The apparatus preferably includes at least two upper sections for processing wafers having diameters greater than 100 mm.

In a preferred form of the invention, a rotatable susceptor is positioned generally horizontally in a processing chamber and one or more spacers extend above the susceptors to support a single wafer spaced from the susceptor. A temperature compensation ring surrounds but is slightly spaced from the susceptor and has a generally rectangular exterior shape. The chamber has at least one process gas inlet and at least one gas outlet for flowing deposition and carrier gas across the upper surface of the wafer, and the chamber has a generally rectangular cross-section generally perpendicular to the gas flow across the wafer and the rectangular ring. An inlet section of the chamber is vertically short and the susceptor and the ring are positioned adjacent the inlet section with the upper surface of the ring and the susceptor being generally in the plane of the lower wall of the inlet section. The ring and the susceptor, together with a wafer mounted on the spacers are heated very uniformly by upper and lower heat sources. With this arrangement, the gas has a generally uniform flow across the width of the chamber since deposition occurs on both the heated ring and the wafer. As a result, carrier gas flow is advantageously reduced from that needed with a circular susceptor and a circular temperature compensation ring wherein it is usually necessary to have increased process gas flow across the center of the wafer and reduced flow across the edges of the wafer in order to obtain uniform deposition on the wafer. The reduced carrier gas flow is particularly desirable because of the reduced cooling effect on the thermally sensitive wafer spaced from the susceptor. It is also desirable that the upper and lower heat sources have a generally rectangular heat pattern that coincides with the shape of the exterior of the rectangular ring so that the heat is principally directed to the area defined by the ring exterior.

In another aspect of the invention the system is provided with the capability to modify the ratio of heat provided by upper and lower heat recesses during the processing of a wafer, so as to promote rapid uniform heating.

With the wafer no longer in contact with the susceptor, the wafer temperature can be maintained uniform even where the susceptor experiences temperature non-uniformities during heat-up and cool-down. In this manner, heat-up and cool-down times can possibly be reduced. Process throughput is thereby increased, as desired. Another aspect of the invention allows for the processing of wafers without the creation of haze or other undesirable effects on the underside of the wafer. This improvement, provided by removing the wafer from contact with the susceptor and bathing its underside with a gas, e.g. hydrogen, is particularly important where double-sided polished wafers are being processed.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view along the longer of two horizontal axes through a reactor chamber incorporating an improved wafer support system of the present invention;

FIG. 2 is a cross-sectional view through one embodiment of a wafer support system of the present invention;

FIG. 2a is a detailed view of one embodiment of a wafer spacer in the form of a pin;

FIG. 2b is a detailed view of an alternative wafer spacer in the form of a sphere;

FIG. 2c is a view of an alternative wafer spacer configuration;

FIG. 3 is an exploded view of the wafer support system illustrated in FIG. 2;

FIG. 4 is a top plan view of an upper section of a segmented susceptor of the wafer support system taken along line 4--4 of FIG. 3;

FIG. 5 is a top plan view of a lower section of the segmented susceptor taken along line 5--5 of FIG. 3;

FIG. 6 is a top plan view of a susceptor support for use in the wafer support system of the present invention, taken along line 6--6 of FIG. 3;

FIG. 7 is a cross-sectional view of another wafer support system according to the present invention;

FIG. 8 is a top plan view of a segmented susceptor for use in the wafer support system of FIG. 7, taken along line 8--8;

FIG. 9 is a top plan view of an alternative upper section of a segmented susceptor having gas outlets distributed around concentric circles;

FIG. 10 is a top plan view of an alternative lower section of a segmented susceptor having multiple gas delivery grooves arranged in concentric circles;

FIG. 11 is a top plan view of a preferred wafer support system of the present invention;

FIG. 12 is a top plan view of a first version of a top section of a segmented susceptor for use in the wafer support system of FIG. 11;

FIG. 13 is a top plan view of a bottom section of the segmented susceptor of the wafer support system of FIG. 11;

FIG. 14 is a cross-sectional view of a captured wafer spacer and purge channel within the segmented susceptor, taken along line 14--14 of FIG. 11;

FIG. 15 is a top plan view of a second version of the top section of the segmented susceptor for use in the wafer support system of FIG. 11;

FIG. 16 is a top plan view of a third version of the top section of the segmented susceptor for use in the wafer support system of FIG. 11;

FIG. 17 is a top plan view of a fourth version of the top section of the segmented susceptor for use in the wafer support system of FIG. 11;

FIG. 18 is a cross-sectional view through another variation of a reactor chamber incorporating the wafer support system of the invention;

FIG. 19 is a top plan view of the chamber of FIG. 18; and

FIG. 20 is a graph showing changes in lamp power ratio during a deposition cycle.

FIG. 21A is a top-plan view of the upper segment of another variation of segmented suscepto